Peter McGoron
67c670cb5c
The PicoRV32 SoC bus generator conflicts with the main SoC bus generator, which causes the address locations in the generated verilog file to be different from the set locations. This code uses custom region classes in soc.py and the Decoder class directly, which is similar to what the finalization of the SoC class uses, and is based on the LiteEth code does. |
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| .. | ||
| rtl | ||
| A7-constraints.xdc | ||
| Makefile | ||
| csr2mp.py | ||
| mmio_descr.py | ||
| soc.py | ||