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Free and open source SoC for Scanning Probe Microscopy
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Peter McGoron 68ce1f4f64 Change SoC IO Region declarations 
LiteX has some distinction between SoCIORegions and SoCRegions that
I don't quite get. SoCRegion has to be cached, SoCIORegion is not
cached. LiteX (Migen?) also does not allow you to reach into
submodules to read values.
 		2024-02-02 23:38:42 +00:00
boot sucessfully boot MAINLINE Linux! 2023-06-05 16:50:08 -04:00
build Fixed bug where scp silently switches to sftp on new version of openssh 2023-08-20 00:47:04 -04:00
buildroot Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00
client Moved network from to 192.168.2 because 192.168.1 is very common 2023-08-08 23:59:34 -04:00
doc use add_constant() to modify network settings in SoC 2024-01-18 10:41:51 -05:00
gateware Change SoC IO Region declarations 2024-02-02 23:38:42 +00:00
linux z output reading 2023-06-27 17:50:55 -04:00
opensbi/litex/vexriscv refactor control loop interface 2023-06-28 17:38:41 -04:00
.gitignore Fixed .gitignore to refer to gateware instead of firmware 2023-08-07 23:50:10 -04:00
README.md Fixed a typo in the top-level README 2023-08-15 17:59:14 -04:00

README.md

upsilon

Upsilon is a 100% free and open source STM/AFM controller for FPGAs running Linux. Read doc/copying/README.md for license information.

Quickstart

Read doc/docker.md to set up the Docker build environment.

Project Organization

  • boot/: This folder is the central place for all built files. This includes the kernel image, rootfs, gateware, etc. This directory also includes everything the TFTP server has to access.
  • build/: Docker build environment.
  • buildroot/: Buildroot configuration files.
  • doc/: Documentation.
  • doc/copying: Licenses.
  • gateware/: FPGA source.
  • gateware/rtl: Verilog sources.
  • gateware/rtl/control_loop: Control loop code.
  • gateware/rtl/spi: SPI code.
  • linux/: Software that runs on the controller.
  • opensbi/: OpenSBI configuration files and source fragments.