Peter McGoron 68ce1f4f64 Change SoC IO Region declarations ... LiteX has some distinction between SoCIORegions and SoCRegions that I don't quite get. SoCRegion has to be cached, SoCIORegion is not cached. LiteX (Migen?) also does not allow you to reach into submodules to read values.		2024-02-02 23:38:42 +00:00
..
rtl	picorv32 integration, take 1	2024-02-02 15:24:18 -05:00
A7-constraints.xdc	firmware is a form of software; gateware is the equivalent for FGPAs	2023-06-14 15:31:49 -04:00
Makefile	use add_constant() to modify network settings in SoC	2024-01-18 10:41:51 -05:00
csr2mp.py	refactor compiles	2023-06-28 18:49:26 -04:00
mmio_descr.py	Fixed spacing in assignment	2023-08-08 17:06:36 -04:00
soc.py	Change SoC IO Region declarations	2024-02-02 23:38:42 +00:00