upsilon/firmware/rtl
Peter McGoron 93c92b9f55 add test scripts for synthesizing ram fifo 2023-03-20 13:57:15 -04:00
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base pass yosys 2023-03-15 17:08:55 -04:00
control_loop pass yosys 2023-03-15 17:08:55 -04:00
raster add test scripts for synthesizing ram fifo 2023-03-20 13:57:15 -04:00
spi pass yosys 2023-03-15 17:08:55 -04:00
waveform pass yosys 2023-03-15 17:08:55 -04:00
Makefile pass yosys 2023-03-15 17:08:55 -04:00
common.makefile pass yosys 2023-03-15 17:08:55 -04:00
testbench.hpp simulate waveform.v 2023-03-15 06:24:28 +00:00
util.hpp test and simulate spi_switch 2023-03-14 15:42:41 +00:00