Peter McGoron
9f76e03028
The previous code did not properly assign all values on all cases, and did not properly assign values (master interfaces, which are poorly named because they are the interfaces to the master, connect to the slave lines directly in the interconnect) |
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| .. | ||
| rtl | ||
| A7-constraints.xdc | ||
| Makefile | ||
| csr2mp.py | ||
| mmio_descr.py | ||
| soc.py | ||