upsilon/firmware/rtl/control_loop
Peter McGoron c21e2bbb63 add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
..
Makefile add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
boothmul.v import updated boothmul 2022-11-11 22:14:50 -05:00
boothmul_sim.cpp import updated boothmul 2022-11-11 22:14:50 -05:00
calculate_dt.v add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
calculate_dt_sim.cpp add calculate dt module with simulation 2022-11-11 22:42:06 -05:00
control_loop.v changes 2022-11-11 21:57:58 -05:00
control_loop_cmds.vh add cycle count for each iteration 2022-10-23 14:21:31 -04:00
control_loop_math.v changes 2022-11-11 21:57:58 -05:00
control_loop_sim.cpp changes 2022-11-11 21:57:58 -05:00
control_loop_sim_top.v changes 2022-11-11 21:57:58 -05:00
intro.md changes 2022-11-11 21:57:58 -05:00
intsat.v add everything im working on 2022-09-16 18:01:34 -04:00
intsat_sim.cpp move simulators to the same directory of the simulated core 2022-10-17 00:45:19 -04:00
mul_const.v changes 2022-11-11 21:57:58 -05:00
mul_const_sim.cpp changes 2022-11-11 21:57:58 -05:00