83 lines
927 B
Verilog
83 lines
927 B
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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//testbench for intsat module
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//Timothy Burman, 2022
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module intsat_testbench
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#(
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parameter IN_LEN = 64,
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parameter LTRUNC = 32
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)
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(
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//Outputs
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output signed [IN_LEN-LTRUNC-1:0] outp
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);
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reg signed [IN_LEN-1:0] inp;
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intsat testbench (inp, outp);
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initial
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begin
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//intial values
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inp = 64'd410000000;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 1;
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#10;
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inp = inp + 10000000;
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#10;
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inp = inp + 10000000;
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#10;
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inp = inp - 1000000;
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#10;
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inp = -64'd1000000000;
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#10;
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inp = inp - 400095;
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#10;
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$finish;
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end
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endmodule |