Peter McGoron f0f1750a9a add ram_fifo_dual_port wrapper to single port FIFO		2022-12-17 10:03:06 -05:00
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control_loop	control_loop: remove reg keyword, yosys doesnt like it	2022-12-17 09:56:26 -05:00
raster	add ram_fifo_dual_port wrapper to single port FIFO	2022-12-17 10:03:06 -05:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00