Peter McGoron
33ec8351d8
Issue was that the ADC cycle half wait (SCK delay) was too fast for the input buffering (since MISO and MOSI are physical inputs and not FPGA wires). |
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|---|---|---|
| .. | ||
| ramp.v | ||
| spi_master.v | ||
| spi_master_no_read.v | ||
| spi_master_no_write.v | ||
| spi_master_ss.v | ||
| spi_master_ss_no_read.v | ||
| spi_master_ss_no_write.v | ||
| spi_master_ss_template.v | ||
| spi_slave.v | ||
| spi_slave_no_read.v | ||
| spi_slave_no_write.v | ||