diff options
| author |  Peter McGoron @ planck
| 2022-10-29 22:20:15 -0400 |
|---|---|---|
| committer | Peter McGoron @ planck
| 2022-10-29 22:20:15 -0400 |
| commit | 89acb17aa0ea50980a680c6fd7c30a05103e09bb (patch) | |
| tree | b374ffcb1cfe98116bc0e329534390b1d80b518b /README.md | |
| parent | write arty SoC generator (diff) | |
succesfully synthesize design
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -5,6 +5,10 @@ Verilog using the [Booth Algorithm][1]. [1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm +This design has been sucessfully synthesized with F4PGA +(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T +running at a clock speed of 100MHz. The test design is in `arty_test`. + ## License All source code is licensed under the CERN-OHL-W v2 or later. |