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| author | 2022-10-29 22:24:51 -0400 | |
|---|---|---|
| committer | 2022-10-29 22:25:39 -0400 | |
| commit | e044843924508c5027d3ecc0f255c0d131e9b320 (patch) | |
| tree | eb4203f0486b9cdad660a692906c5c25f3d86ee6 /arty_test/README.md | |
| parent | succesfully synthesize design (diff) | |
documentation and license
Diffstat (limited to 'arty_test/README.md')
| -rw-r--r-- | arty_test/README.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arty_test/README.md b/arty_test/README.md new file mode 100644 index 0000000..a703e75 --- /dev/null +++ b/arty_test/README.md @@ -0,0 +1,13 @@ +This test requires LiteX 2022.08. You will need to define `DEBUG` in the `boothmul.v` +file for the logic analyzer to work correctly. + +Run `python3 soc.py` to build the design. Afterwards, load the design. Then run + + litex_server --uart --uart-port /dev/ttyUSB1 + +afterwards run + + python3 hardtest.py + +This will generate two .vcd files, which you can check to verify that the multiplier +is working. |
