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authorGravatar Peter McGoron 2023-02-11 20:51:03 +0000
committerGravatar Peter McGoron 2023-02-11 20:51:03 +0000
commit70720b8a1610a9e8dc43a9735af43b4a481153e9 (patch)
tree28475d2edcce9214a9e8e2e2714f7bd1215735e4 /asm
parentadd signed division IDIV (diff)
rename idiv to sdiv
Diffstat (limited to 'asm')
-rw-r--r--asm/creole.py2
-rw-r--r--asm/test.py10
2 files changed, 6 insertions, 6 deletions
diff --git a/asm/creole.py b/asm/creole.py
index 3746003..1d98051 100644
--- a/asm/creole.py
+++ b/asm/creole.py
@@ -91,7 +91,7 @@ class Instruction(Enum):
ADD = 3, ArgType.REG, ArgType.VAL, ArgType.VAL
MUL = 4, ArgType.REG, ArgType.VAL, ArgType.VAL
DIV = 5, ArgType.REG, ArgType.VAL, ArgType.VAL
- IDIV = 6, ArgType.REG, ArgType.VAL, ArgType.VAL
+ SDIV = 6, ArgType.REG, ArgType.VAL, ArgType.VAL
JL = 7, ArgType.LAB, ArgType.VAL, ArgType.VAL
CLB = 8, ArgType.LAB
SYS = 9, ArgType.VAL
diff --git a/asm/test.py b/asm/test.py
index 1274d9c..4b6471c 100644
--- a/asm/test.py
+++ b/asm/test.py
@@ -267,16 +267,16 @@ class DivTest(unittest.TestCase):
ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.DIVIDE_BY_ZERO)
- def test_idiv_by_zero(self):
+ def test_sdiv_by_zero(self):
p = Program()
- p.parse_asm_line("idiv r0 8 0")
+ p.parse_asm_line("sdiv r0 8 0")
ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.DIVIDE_BY_ZERO)
- def test_div_neg(self):
+ def test_sdiv_neg(self):
p = Program()
- p.parse_asm_line("idiv r0 16 -4")
- p.parse_asm_line("idiv r1 r0 -4")
+ p.parse_asm_line("sdiv r0 16 -4")
+ p.parse_asm_line("sdiv r1 r0 -4")
ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0), -4)