108 lines
2.4 KiB
Coq
108 lines
2.4 KiB
Coq
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/* Booth Multiplication
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* Written by Peter McGoron, 2022.
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*/
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module boothmul
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#(
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parameter A1_LEN = 32,
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parameter A2_LEN = 32,
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// AZLEN_SIZ = floor(log2(A2_LEN + 2) + 1).
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// It must be able to store A2_LEN + 2.
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parameter A2LEN_SIZ = 6
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)
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(
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input clk,
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input arm,
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input [A1_LEN-1:0] a1,
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input [A2_LEN-1:0] a2,
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output [A1_LEN+A2_LEN-1:0] outn,
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output reg fin
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);
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/***********************
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* Booth Parameters
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**********************/
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localparam OUT_LEN = A1_LEN + A2_LEN;
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localparam REG_LEN = OUT_LEN + 2;
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/* The Booth multiplication algorithm is a sequential algorithm for
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* twos-compliment integers.
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*
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* Let REG_LEN be equal to 1 + len(a1) + len(a2) + 1.
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* Let P, S, and A be of length REG_LEN.
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* Let A = a1 << len(a2) + 1, where a1 sign extends to the upper bit.
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* Let S = -a1 << len(a2) + 1, where a1 sign extens to the upper bit.
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* Let P = a2 << 1.
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*
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* Repeat the following len(a2) times:
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* case(P[1:0])
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* 2'b00, 2'b11: P <= P >>> 1;
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* 2'b01: P <= (P + A) >>> 1;
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* 2'b10: P <= (P + S) >>> 1;
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* endcase
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* The final value is P[REG_LEN-2:1].
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*
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* Wires and registers of REG_LEN length are organized like:
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*
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* /Overflow bit
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* [M][ REG_LEN ][0]
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* [M][ A1_LEN ][ A2_LEN ][0]
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*/
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reg signed [REG_LEN-1:0] a;
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reg signed [REG_LEN-1:0] s;
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reg signed [REG_LEN-1:0] p = 0;
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assign outn[OUT_LEN-1:0] = p[REG_LEN-2:1];
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/**********************
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* Loop Implementation
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*********************/
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reg[A2LEN_SIZ-1:0] loop_accul = 0;
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always @ (posedge clk) begin
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if (!arm) begin
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loop_accul <= 0;
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fin <= 0;
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end else if (loop_accul == 0) begin
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p[0] <= 0;
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p[A2_LEN:1] <= a2;
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p[REG_LEN-1:A2_LEN+1] <= 0;
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a[A2_LEN:0] <= 0;
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a[REG_LEN-2:A2_LEN + 1] <= a1;
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a[REG_LEN-1] <= a1[A1_LEN-1]; // Sign extension
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s[A2_LEN:0] <= 0;
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// Extend before negation to ensure size
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s[REG_LEN-1:A2_LEN+1] <= ~{a1[A1_LEN-1],a1} + 1;
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loop_accul <= loop_accul + 1;
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end else if (loop_accul < A2_LEN + 1) begin
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/* The loop counter starts from 1, so it must go to
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* A2_LEN + 1 exclusive.
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* (i = 0; i < len; i++)
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* becomes (i = 1; i < len + 1; i++)
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*/
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loop_accul <= loop_accul + 1;
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case (p[1:0])
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2'b00, 2'b11: p <= p >>> 1;
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2'b10: p <= (p + s) >>> 1;
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2'b01: p <= (p + a) >>> 1;
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endcase
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end else begin
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fin <= 1;
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end
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end
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`ifdef BOOTH_SIM
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initial begin
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$dumpfile("booth.vcd");
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$dumpvars;
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end
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`endif
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endmodule
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