succesfully synthesize design
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@ -5,6 +5,10 @@ Verilog using the [Booth Algorithm][1].
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[1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
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This design has been sucessfully synthesized with F4PGA
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(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
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running at a clock speed of 100MHz. The test design is in `arty_test`.
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## License
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All source code is licensed under the CERN-OHL-W v2 or later.
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160
arty_test/soc.py
160
arty_test/soc.py
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@ -1,38 +1,138 @@
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# Construct SoC.
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# This file is licensed under the BSD 2 Clause License.
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# (c) Peter McGoron 2022
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from migen import ClockSignal
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from litex_boards.targets.digilent_arty import BaseSoC
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from litex_boards.platforms.digilent_arty import Platform, Builder
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from litescope import LiteScopeAnalyzer
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from migen import *
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litex_boards.platforms.digilent_arty import Platform
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import math
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platform = Platform(variant="a7-100")
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platform.add_source("../boothmul.v")
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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class TestPlatform(BaseSoC):
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def __init__(self, platform, constwid = 48, inwid = 48):
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BaseSoC.__init__(
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with_uartbone = True,
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toolchain = "symbiflow",
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platform = platform
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# Clock and Reset Generator
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class Multiplier(Module, AutoCSR):
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def __init__(self, constwid = 48, inwid = 48):
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a2lensiz = math.ceil(math.log2(inwid) + 1) + 1
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self.const_in = CSRStorage(constwid, description="Multiplier Constant")
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self.inval = CSRStorage(inwid, description="Multiplier 2nd Input")
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self.outval = CSRStatus(constwid + inwid, description="Multiplier Output")
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self.p = CSRStatus(constwid + inwid + 2, description="P")
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self.a = CSRStatus(constwid + inwid + 2, description="A")
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self.s = CSRStatus(constwid + inwid + 2, description="S")
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self.state = CSRStatus(a2lensiz, description="State")
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self.arm = CSRStorage(1, description="Arm")
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self.fin = CSRStatus(1, description="Multiplier Finished")
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self.specials += Instance("boothmul",
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p_A1_LEN = constwid,
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p_A2_LEN = inwid,
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p_A2LEN_SIZ = math.ceil(math.log2(inwid) + 1) + 1,
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i_clk = ClockSignal("sys"),
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i_a1 = self.const_in.storage,
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i_a2 = self.inval.storage,
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o_outn = self.outval.status,
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i_arm = self.arm.storage,
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o_fin = self.fin.status,
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o_debug_a = self.a.status,
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o_debug_s = self.s.status,
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o_debug_p = self.p.status,
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o_debug_state = self.state.status
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)
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self.const_in = CSRStorage(constwid)
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self.inval = CSRStorage(inwid)
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self.outval = CSRStatus(const_wid + inwid)
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self.arm = CSRStorage(arm)
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self.fin = CSRStatus(arm)
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self.specials += Instance("boothmul",
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p_A1_LEN = constwid,
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p_A2_LEN = inwid,
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A2LEN_SIZ = math.ceil(math.log2(inwid) + 1) + 1,
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clk = ClockSignal(),
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a1 = self.const_in.storage,
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a2 = self.inval.storage,
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outn = self.outval.status,
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i_arm = self.arm.storage,
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fin = self.fin.status
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)
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class TestPlatform(SoCCore, AutoCSR):
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def __init__(self, platform, constwid = 8, inwid = 8):
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sys_clk_freq = int(100e6)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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cpu_type = None,
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integrated_sram_size = 0x2000,
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with_uart = False,
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platform = platform
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)
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from litescope import LiteScopeAnalyzer
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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self.submodules.multiplier = Multiplier(constwid, inwid)
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self.add_uartbone(name="serial", baudrate=115200)
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self.submodules.analyzer = LiteScopeAnalyzer(
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[
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self.multiplier.p.status,
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self.multiplier.a.status,
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self.multiplier.s.status,
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self.multiplier.inval.storage,
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self.multiplier.const_in.storage,
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self.multiplier.outval.status,
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self.multiplier.arm.storage,
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self.multiplier.fin.status,
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self.multiplier.state.status,
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], depth=64, clock_domain = "sys", samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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platform = Platform(variant="a7-35", toolchain="symbiflow")
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platform.add_source("../boothmul.v")
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builder = Builder(TestPlatform(platform), csr_csv="csr.csv")
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builder.build()
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59
boothmul.v
59
boothmul.v
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@ -1,3 +1,4 @@
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`define DEBUG
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/* Booth Multiplication v0.1
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* Written by Peter McGoron, 2022.
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*
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@ -29,6 +30,12 @@ module boothmul
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input [A1_LEN-1:0] a1,
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input [A2_LEN-1:0] a2,
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output [A1_LEN+A2_LEN-1:0] outn,
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`ifdef DEBUG
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output [A1_LEN+A2_LEN+1:0] debug_a,
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output [A1_LEN+A2_LEN+1:0] debug_s,
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output [A1_LEN+A2_LEN+1:0] debug_p,
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output [A2LEN_SIZ-1:0] debug_state,
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`endif
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output reg fin
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);
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@ -36,8 +43,8 @@ module boothmul
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* Booth Parameters
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**********************/
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localparam OUT_LEN = A1_LEN + A2_LEN;
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localparam REG_LEN = OUT_LEN + 2;
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`define OUT_LEN (A1_LEN + A2_LEN)
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`define REG_LEN (`OUT_LEN + 2)
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/* The Booth multiplication algorithm is a sequential algorithm for
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* twos-compliment integers.
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@ -63,11 +70,26 @@ localparam REG_LEN = OUT_LEN + 2;
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* [M][ A1_LEN ][ A2_LEN ][0]
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*/
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reg signed [REG_LEN-1:0] a;
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reg signed [REG_LEN-1:0] s;
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reg signed [REG_LEN-1:0] p = 0;
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reg [A1_LEN-1:0] a1_reg;
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assign outn[OUT_LEN-1:0] = p[REG_LEN-2:1];
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wire [`REG_LEN-1:0] a;
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assign a[A2_LEN:0] = 0;
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assign a[`REG_LEN-2:A2_LEN+1] = a1_reg;
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assign a[`REG_LEN-1] = a1_reg[A1_LEN-1];
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wire signed [`REG_LEN-1:0] a_signed;
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assign a_signed = a;
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wire [`REG_LEN-1:0] s;
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assign s[A2_LEN:0] = 0;
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assign s[`REG_LEN-1:A2_LEN+1] = ~{a1_reg[A1_LEN-1],a1_reg} + 1;
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wire signed [`REG_LEN-1:0] s_signed;
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assign s_signed = s;
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reg [`REG_LEN-1:0] p;
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wire signed [`REG_LEN-1:0] p_signed;
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assign p_signed = p;
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assign outn = p[`REG_LEN-2:1];
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/**********************
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* Loop Implementation
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@ -75,6 +97,13 @@ assign outn[OUT_LEN-1:0] = p[REG_LEN-2:1];
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reg[A2LEN_SIZ-1:0] loop_accul = 0;
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`ifdef DEBUG
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assign debug_a = a;
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assign debug_s = s;
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assign debug_p = p;
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assign debug_state = loop_accul;
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`endif
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always @ (posedge clk) begin
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if (!arm) begin
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loop_accul <= 0;
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@ -82,18 +111,14 @@ always @ (posedge clk) begin
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end else if (loop_accul == 0) begin
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p[0] <= 0;
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p[A2_LEN:1] <= a2;
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p[REG_LEN-1:A2_LEN+1] <= 0;
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p[`REG_LEN-1:A2_LEN+1] <= 0;
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a[A2_LEN:0] <= 0;
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a[REG_LEN-2:A2_LEN + 1] <= a1;
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a[REG_LEN-1] <= a1[A1_LEN-1]; // Sign extension
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s[A2_LEN:0] <= 0;
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// Extend before negation to ensure size
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s[REG_LEN-1:A2_LEN+1] <= ~{a1[A1_LEN-1],a1} + 1;
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a1_reg <= a1;
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loop_accul <= loop_accul + 1;
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/* verilator lint_off WIDTH */
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end else if (loop_accul < A2_LEN + 1) begin
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/* verilator lint_on WIDTH */
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/* The loop counter starts from 1, so it must go to
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* A2_LEN + 1 exclusive.
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* (i = 0; i < len; i++)
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@ -101,9 +126,9 @@ always @ (posedge clk) begin
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*/
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loop_accul <= loop_accul + 1;
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case (p[1:0])
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2'b00, 2'b11: p <= p >>> 1;
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2'b10: p <= (p + s) >>> 1;
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2'b01: p <= (p + a) >>> 1;
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2'b00, 2'b11: p <= p_signed >>> 1;
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2'b10: p <= (p_signed + s_signed) >>> 1;
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2'b01: p <= (p_signed + a_signed) >>> 1;
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endcase
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end else begin
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fin <= 1;
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