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Verilog Booth Multiplier
4 Commits 2 Branches 2 Tags 245 KiB
Python 58.3%
Verilog 27.2%
C++ 11.6%
Makefile 2.9%
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Peter McGoron @ planck 89acb17aa0 succesfully synthesize design 2022-10-29 22:20:15 -04:00
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README.md

Booth Multiplier

Sequentially multiply two signed twos-compliment integers in Verilog using the Booth Algorithm.

This design has been sucessfully synthesized with F4PGA (5aafae65883e95e41de2d0294729662dbe0a34f5) on a Digilent Arty A7-35T running at a clock speed of 100MHz. The test design is in arty_test.

License

All source code is licensed under the CERN-OHL-W v2 or later.

Usage

Set parameters A1_LEN and A2_LEN to the argument size of the first and second integer. Set A2LEN_SIZ equal to floor(log2(A2_LEN) + 1).

After inputting each integer, pulse arm and wait until fin goes high to retreive the output in outn.

Simulating

Simulation is done with Verilator. Run make.