145 lines
3.5 KiB
Verilog
145 lines
3.5 KiB
Verilog
/* Booth Multiplication v1.0
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* Written by Peter McGoron, 2022.
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*
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* This source describes Open Hardware and is licensed under the
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* CERN-OHL-W v2.
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* You may redistribute and modify this documentation and make products using
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* it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl), or, at
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* your option, any later version.
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*
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,
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* INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR
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* A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2 for applicable
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* conditions.
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*
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* Source location: https://software.mcgoron.com/peter/boothmul
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*/
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module boothmul
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#(
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parameter A1_LEN = 32,
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parameter A2_LEN = 32,
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// AZLEN_SIZ = floor(log2(A2_LEN + 2) + 1).
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// It must be able to store A2_LEN + 2.
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parameter A2LEN_SIZ = 6
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)
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(
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input clk,
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input arm,
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input [A1_LEN-1:0] a1,
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input [A2_LEN-1:0] a2,
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output [A1_LEN+A2_LEN-1:0] outn,
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`ifdef DEBUG
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output [A1_LEN+A2_LEN+1:0] debug_a,
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output [A1_LEN+A2_LEN+1:0] debug_s,
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output [A1_LEN+A2_LEN+1:0] debug_p,
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output [A2LEN_SIZ-1:0] debug_state,
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`endif
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output reg fin
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);
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/***********************
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* Booth Parameters
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**********************/
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`define OUT_LEN (A1_LEN + A2_LEN)
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`define REG_LEN (`OUT_LEN + 2)
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/* The Booth multiplication algorithm is a sequential algorithm for
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* twos-compliment integers.
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*
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* Let REG_LEN be equal to 1 + len(a1) + len(a2) + 1.
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* Let P, S, and A be of length REG_LEN.
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* Let A = a1 << len(a2) + 1, where a1 sign extends to the upper bit.
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* Let S = -a1 << len(a2) + 1, where a1 sign extens to the upper bit.
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* Let P = a2 << 1.
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*
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* Repeat the following len(a2) times:
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* case(P[1:0])
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* 2'b00, 2'b11: P <= P >>> 1;
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* 2'b01: P <= (P + A) >>> 1;
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* 2'b10: P <= (P + S) >>> 1;
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* endcase
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* The final value is P[REG_LEN-2:1].
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*
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* Wires and registers of REG_LEN length are organized like:
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*
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* /Overflow bit
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* [M][ REG_LEN ][0]
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* [M][ A1_LEN ][ A2_LEN ][0]
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*/
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reg [A1_LEN-1:0] a1_reg;
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wire [`REG_LEN-1:0] a;
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assign a[A2_LEN:0] = 0;
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assign a[`REG_LEN-2:A2_LEN+1] = a1_reg;
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assign a[`REG_LEN-1] = a1_reg[A1_LEN-1];
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wire signed [`REG_LEN-1:0] a_signed;
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assign a_signed = a;
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wire [`REG_LEN-1:0] s;
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assign s[A2_LEN:0] = 0;
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assign s[`REG_LEN-1:A2_LEN+1] = ~{a1_reg[A1_LEN-1],a1_reg} + 1;
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wire signed [`REG_LEN-1:0] s_signed;
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assign s_signed = s;
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reg [`REG_LEN-1:0] p;
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wire signed [`REG_LEN-1:0] p_signed;
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assign p_signed = p;
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assign outn = p[`REG_LEN-2:1];
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/**********************
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* Loop Implementation
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*********************/
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reg[A2LEN_SIZ-1:0] loop_accul = 0;
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`ifdef DEBUG
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assign debug_a = a;
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assign debug_s = s;
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assign debug_p = p;
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assign debug_state = loop_accul;
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`endif
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always @ (posedge clk) begin
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if (!arm) begin
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loop_accul <= 0;
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fin <= 0;
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end else if (loop_accul == 0) begin
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p[0] <= 0;
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p[A2_LEN:1] <= a2;
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p[`REG_LEN-1:A2_LEN+1] <= 0;
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a1_reg <= a1;
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loop_accul <= loop_accul + 1;
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/* verilator lint_off WIDTH */
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end else if (loop_accul < A2_LEN + 1) begin
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/* verilator lint_on WIDTH */
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/* The loop counter starts from 1, so it must go to
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* A2_LEN + 1 exclusive.
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* (i = 0; i < len; i++)
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* becomes (i = 1; i < len + 1; i++)
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*/
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loop_accul <= loop_accul + 1;
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case (p[1:0])
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2'b00, 2'b11: p <= p_signed >>> 1;
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2'b10: p <= (p_signed + s_signed) >>> 1;
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2'b01: p <= (p_signed + a_signed) >>> 1;
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endcase
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end else begin
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fin <= 1;
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end
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end
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`ifdef BOOTH_SIM
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initial begin
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$dumpfile("booth.vcd");
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$dumpvars;
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end
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`endif
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endmodule
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