Verilog Booth Multiplier
Go to file
Peter McGoron a70737a671 license and bump version 2022-10-29 22:26:51 -04:00
arty_test documentation and license 2022-10-29 22:25:39 -04:00
.gitignore add .gitignore 2022-10-29 22:26:10 -04:00
COPYING bump version 2022-10-23 04:42:35 -04:00
Makefile Booth multiplier 2022-08-09 18:13:47 -04:00
README.md license and bump version 2022-10-29 22:26:51 -04:00
boothmul.v license and bump version 2022-10-29 22:26:51 -04:00
sim.cpp succesfully synthesize design 2022-10-29 22:20:15 -04:00

README.md

Booth Multiplier

Sequentially multiply two signed twos-compliment integers in Verilog using the Booth Algorithm.

This design has been sucessfully synthesized with F4PGA (5aafae65883e95e41de2d0294729662dbe0a34f5) on a Digilent Arty A7-35T running at a clock speed of 100MHz. The test design is in arty_test.

License

All source code is licensed under the CERN-OHL-W v2 or later, unless otherwise noted.

Usage

Set parameters A1_LEN and A2_LEN to the argument size of the first and second integer. Set A2LEN_SIZ equal to floor(log2(A2_LEN) + 1).

After inputting each integer, pulse arm and wait until fin goes high to retreive the output in outn.

Simulating

Simulation is done with Verilator. Run make.