boothmul/arty_test
Peter McGoron e044843924 documentation and license 2022-10-29 22:25:39 -04:00
..
README.md documentation and license 2022-10-29 22:25:39 -04:00
hardtest.py documentation and license 2022-10-29 22:25:39 -04:00
soc.py succesfully synthesize design 2022-10-29 22:20:15 -04:00

README.md

This test requires LiteX 2022.08. You will need to define DEBUG in the boothmul.v file for the logic analyzer to work correctly.

Run python3 soc.py to build the design. Afterwards, load the design. Then run

litex_server --uart --uart-port /dev/ttyUSB1

afterwards run

python3 hardtest.py

This will generate two .vcd files, which you can check to verify that the multiplier is working.