add ready_to_arm to indiciate when the module can accept another command

This commit is contained in:
Peter McGoron 2023-04-20 16:23:23 +00:00
parent 6459fc5c2a
commit 2119ec275b
4 changed files with 28 additions and 2 deletions

View File

@ -40,6 +40,7 @@ spi_master
`endif `endif
output reg sck_wire, output reg sck_wire,
output reg finished, output reg finished,
output reg ready_to_arm,
input arm input arm
); );
@ -134,17 +135,28 @@ task cycle_change();
end end
endtask endtask
initial ready_to_arm = 1;
always @ (posedge clk) begin always @ (posedge clk) begin
case (state) case (state)
WAIT_ON_ARM: begin WAIT_ON_ARM: begin
`ifdef SIMULATION
if (!ready_to_arm)
$error("not ready to arm in wait_on_arm");
`endif
if (!arm) begin if (!arm) begin
idle_state(); idle_state();
finished <= 0; finished <= 0;
end else begin end else begin
setup_bits(); setup_bits();
ready_to_arm <= 0;
end end
end end
ON_CYCLE: begin ON_CYCLE: begin
`ifdef SIMULATION
if (ready_to_arm)
$error("ready_to_arm while on cycle");
`endif
if (sck) begin // rising edge if (sck) begin // rising edge
if (PHASE == 1) begin if (PHASE == 1) begin
write_data(); write_data();
@ -174,6 +186,10 @@ always @ (posedge clk) begin
end end
end end
CYCLE_WAIT: begin CYCLE_WAIT: begin
`ifdef SIMULATION
if (ready_to_arm)
$error("ready_to_arm while in cycle wait");
`endif
if (timer == CYCLE_HALF_WAIT) begin if (timer == CYCLE_HALF_WAIT) begin
timer <= 1; timer <= 1;
cycle_change(); cycle_change();
@ -182,10 +198,15 @@ always @ (posedge clk) begin
end end
end end
WAIT_FINISHED: begin WAIT_FINISHED: begin
`ifdef SIMULATION
if (ready_to_arm)
$error("ready_to_arm while in wait finished");
`endif
finished <= 1; finished <= 1;
idle_state(); idle_state();
if (!arm) begin if (!arm) begin
state <= WAIT_ON_ARM; state <= WAIT_ON_ARM;
ready_to_arm <= 1;
end end
end end
endcase endcase

View File

@ -27,6 +27,7 @@ module `SPI_MASTER_SS_NAME
`endif `endif
output sck_wire, output sck_wire,
output finished, output finished,
output ready_to_arm,
output ss_L, output ss_L,
input arm input arm
); );
@ -54,6 +55,7 @@ assign ss_L = !ss;
`endif `endif
.sck_wire(sck_wire), .sck_wire(sck_wire),
.finished(finished), .finished(finished),
.ready_to_arm(ready_to_arm),
.arm(arm_master) .arm(arm_master)
); );

View File

@ -19,6 +19,7 @@ run_test() {
-GWID_LEN=$WIDLEN \ -GWID_LEN=$WIDLEN \
-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \ -DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
-DVCDFILE="\"$DIR.fst\"" \ -DVCDFILE="\"$DIR.fst\"" \
-DSIMULATION \
--Mdir $DIR \ --Mdir $DIR \
$EXTARG \ $EXTARG \
simtop.v write_read.cpp $MODS \ simtop.v write_read.cpp $MODS \

View File

@ -26,6 +26,7 @@ module simtop
`endif `endif
input rdy, input rdy,
output master_finished, output master_finished,
output ready_to_arm,
output err output err
); );
@ -74,6 +75,7 @@ reg slave_error;
`endif `endif
.sck_wire(sck), .sck_wire(sck),
.finished(master_finished), .finished(master_finished),
.ready_to_arm(ready_to_arm),
.arm(activate) .arm(activate)
); );
@ -99,11 +101,11 @@ reg slave_error;
.err(err) .err(err)
); );
/* `ifdef SIMULATION
initial begin initial begin
$dumpfile(`VCDFILE); $dumpfile(`VCDFILE);
$dumpvars; $dumpvars;
end end
*/ `endif
endmodule endmodule