add ready_to_arm to indiciate when the module can accept another command
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6459fc5c2a
commit
2119ec275b
21
spi_master.v
21
spi_master.v
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@ -40,6 +40,7 @@ spi_master
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`endif
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`endif
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output reg sck_wire,
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output reg sck_wire,
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output reg finished,
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output reg finished,
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output reg ready_to_arm,
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input arm
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input arm
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);
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);
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@ -134,17 +135,28 @@ task cycle_change();
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end
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end
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endtask
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endtask
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initial ready_to_arm = 1;
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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case (state)
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case (state)
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WAIT_ON_ARM: begin
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WAIT_ON_ARM: begin
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`ifdef SIMULATION
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if (!ready_to_arm)
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$error("not ready to arm in wait_on_arm");
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`endif
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if (!arm) begin
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if (!arm) begin
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idle_state();
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idle_state();
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finished <= 0;
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finished <= 0;
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end else begin
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end else begin
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setup_bits();
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setup_bits();
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ready_to_arm <= 0;
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end
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end
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end
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end
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ON_CYCLE: begin
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ON_CYCLE: begin
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`ifdef SIMULATION
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if (ready_to_arm)
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$error("ready_to_arm while on cycle");
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`endif
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if (sck) begin // rising edge
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if (sck) begin // rising edge
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if (PHASE == 1) begin
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if (PHASE == 1) begin
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write_data();
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write_data();
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@ -174,6 +186,10 @@ always @ (posedge clk) begin
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end
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end
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end
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end
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CYCLE_WAIT: begin
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CYCLE_WAIT: begin
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`ifdef SIMULATION
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if (ready_to_arm)
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$error("ready_to_arm while in cycle wait");
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`endif
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if (timer == CYCLE_HALF_WAIT) begin
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if (timer == CYCLE_HALF_WAIT) begin
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timer <= 1;
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timer <= 1;
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cycle_change();
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cycle_change();
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@ -182,10 +198,15 @@ always @ (posedge clk) begin
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end
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end
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end
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end
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WAIT_FINISHED: begin
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WAIT_FINISHED: begin
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`ifdef SIMULATION
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if (ready_to_arm)
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$error("ready_to_arm while in wait finished");
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`endif
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finished <= 1;
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finished <= 1;
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idle_state();
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idle_state();
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if (!arm) begin
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if (!arm) begin
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state <= WAIT_ON_ARM;
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state <= WAIT_ON_ARM;
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ready_to_arm <= 1;
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end
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end
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end
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end
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endcase
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endcase
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@ -27,6 +27,7 @@ module `SPI_MASTER_SS_NAME
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`endif
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`endif
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output sck_wire,
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output sck_wire,
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output finished,
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output finished,
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output ready_to_arm,
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output ss_L,
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output ss_L,
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input arm
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input arm
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);
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);
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@ -54,6 +55,7 @@ assign ss_L = !ss;
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`endif
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`endif
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.sck_wire(sck_wire),
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.sck_wire(sck_wire),
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.finished(finished),
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.finished(finished),
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.ready_to_arm(ready_to_arm),
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.arm(arm_master)
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.arm(arm_master)
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);
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);
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@ -19,6 +19,7 @@ run_test() {
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-GWID_LEN=$WIDLEN \
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-GWID_LEN=$WIDLEN \
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-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
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-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
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-DVCDFILE="\"$DIR.fst\"" \
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-DVCDFILE="\"$DIR.fst\"" \
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-DSIMULATION \
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--Mdir $DIR \
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--Mdir $DIR \
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$EXTARG \
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$EXTARG \
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simtop.v write_read.cpp $MODS \
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simtop.v write_read.cpp $MODS \
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@ -26,6 +26,7 @@ module simtop
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`endif
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`endif
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input rdy,
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input rdy,
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output master_finished,
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output master_finished,
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output ready_to_arm,
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output err
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output err
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);
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);
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@ -74,6 +75,7 @@ reg slave_error;
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`endif
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`endif
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.sck_wire(sck),
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.sck_wire(sck),
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.finished(master_finished),
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.finished(master_finished),
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.ready_to_arm(ready_to_arm),
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.arm(activate)
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.arm(activate)
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);
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);
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@ -99,11 +101,11 @@ reg slave_error;
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.err(err)
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.err(err)
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);
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);
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/*
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`ifdef SIMULATION
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initial begin
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initial begin
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$dumpfile(`VCDFILE);
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$dumpfile(`VCDFILE);
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$dumpvars;
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$dumpvars;
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end
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end
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*/
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`endif
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endmodule
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endmodule
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