add read only master with tests

spi_master.v

@@ -3,7 +3,18 @@
  * License, v.2.0. If a copy of the MPL was not distributed with this
  * file, You can obtain one at https://mozilla.org/MPL/2.0/.
  */
-module spi_master
+
+module
+`ifdef SPI_MASTER_NO_READ
+spi_master_no_read
+`else
+`ifdef SPI_MASTER_NO_WRITE
+spi_master_no_write
+`else
+spi_master
+`endif
+`endif
+
 #(
 	parameter WID = 24, // Width of bits per transaction.
 	parameter WID_LEN = 5, // Length in bits required to store WID
@@ -78,11 +89,15 @@ task setup_bits();
 	 * For mode 01 and mode 10, the first action is a WRITE.
 	 */
 	if (POLARITY == PHASE) begin
+`ifndef SPI_MASTER_NO_WRITE
 		mosi <= to_slave[WID-1];
 		send_buf <= to_slave << 1;
+`endif
 		state <= CYCLE_WAIT;
 	end else begin
+`ifndef SPI_MASTER_NO_WRITE
 		send_buf <= to_slave;
+`endif
 		state <= ON_CYCLE;
 	end
 endtask

spi_master_no_write.v

@@ -0,0 +1,3 @@
+`define SPI_MASTER_NO_WRITE
+/* verilator lint_off DECLFILENAME */
+`include "spi_master.v"

spi_slave.v

@@ -3,7 +3,15 @@
  * License, v.2.0. If a copy of the MPL was not distributed with this
  * file, You can obtain one at https://mozilla.org/MPL/2.0/.
  */
-module spi_slave
+
+module
+`ifdef SPI_SLAVE_NO_READ
+spi_slave_no_read
+`elsif SPI_SLAVE_NO_WRITE
+spi_slave_no_write
+`else
+spi_slave
+`endif
 #(
 	parameter WID = 24, // Width of bits per transaction.
 	parameter WID_LEN = 5, // Length in bits required to store WID
@@ -16,15 +24,15 @@ module spi_slave
 	input ss_L,
 `ifndef SPI_SLAVE_NO_READ
 	output reg [WID-1:0] from_master,
-	input mosi,
+	input reg mosi,
 `endif
 `ifndef SPI_SLAVE_NO_WRITE
 	input [WID-1:0] to_master,
-	output miso,
+	output reg miso,
 `endif
-	output finished,
+	output reg finished,
 	input rdy,
-	output err
+	output reg err
 );
 
 wire ss = !ss_L;
@@ -52,6 +60,7 @@ task write_data();
 endtask
 
 task setup_bits();
+`ifndef SPI_SLAVE_NO_WRITE
 	/* at Mode 00, the transmission starts with
 	 * a rising edge, and at mode 11, it starts with a falling
 	 * edge. For both modes, these are READs.
@@ -64,6 +73,7 @@ task setup_bits();
 	end else begin
 		send_buf <= to_master;
 	end
+`endif
 endtask
 
 task check_counter();

spi_slave_no_read.v

@@ -0,0 +1,3 @@
+`define SPI_SLAVE_NO_READ
+/* verilator lint_off DECLFILENAME */
+`include "spi_slave.v"

tests/Makefile

@@ -3,7 +3,8 @@ MODES=00 01 10 11
 all:
 	for i in ${MODES}; do \
 		make -f run_mode.makefile MODE="$$i"; \
+		make -f run_mode.makefile MODE="$$i" PREFIX="read_only_" MASTER_TYPE="_no_write" SLAVE_TYPE="_no_read"; \
 	done
 
 clean:
-	rm -rf obj_dir mode[01][01]*
+	rm -rf obj_dir mode[01][01]* read_only_mode[01][01]*

tests/read_only_mode_template.cpp

@@ -0,0 +1,4 @@
+#include "Vread_only_mode@MODE@.h"
+using TopModule = Vread_only_mode@MODE@;
+#define READ_ONLY
+#include "write_read.cpp"

tests/read_only_mode_template.v

@@ -0,0 +1,57 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module read_only_mode@MODE@ (
+	input clk,
+	input activate,
+	input ss,
+	input rdy,
+	output master_finished
+);
+
+wire miso;
+wire sck;
+wire ss_L = !ss;
+reg [23:0] from_slave_data;
+reg finished;
+reg err;
+
+spi_master_no_write
+#(
+	.POLARITY(@POLARITY@),
+	.PHASE(@PHASE@)
+) master (
+	.clk(clk),
+	.from_slave(from_slave_data),
+	.miso(miso),
+	.sck_wire(sck),
+	.finished(master_finished),
+	.arm(activate)
+);
+
+reg [23:0] to_master = 24'hF4325F;
+
+spi_slave_no_read
+#(
+	.POLARITY(@POLARITY@),
+	.PHASE(@PHASE@)
+) slave (
+	.clk(clk),
+	.sck(sck),
+	.ss_L(ss_L),
+	.to_master(to_master),
+	.miso(miso),
+	.finished(finished),
+	.rdy(rdy),
+	.err(finished)
+);
+
+initial begin
+	$dumpfile("read_only_mode@MODE@.vcd");
+	$dumpvars();
+end
+
+endmodule

tests/run_mode.makefile

@@ -3,8 +3,8 @@
 # License, v.2.0. If a copy of the MPL was not distributed with this
 # file, You can obtain one at https://mozilla.org/MPL/2.0/.
 
-TESTBENCH_BASE=mode${MODE}
+TESTBENCH_BASE=${PREFIX}mode${MODE}
-AUXFILES=../spi_master.v ../spi_slave.v
+AUXFILES=../spi_master${MASTER_TYPE}.v ../spi_slave${SLAVE_TYPE}.v
 
 CPP_TESTBENCH=${TESTBENCH_BASE}.cpp
 WAVEFILE=${TESTBENCH_BASE}.vcd
@@ -15,10 +15,10 @@ ${WAVEFILE}: obj_dir/V${TESTBENCH_BASE}
 	./obj_dir/V${TESTBENCH_BASE}
 
 obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
-	verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
+	verilator -I.. -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
 obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
 	make -C obj_dir -f V${TESTBENCH_BASE}.mk
 ${TESTBENCH_BASE}.v: mode_template.v
-	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" mode_template.v > ${TESTBENCH_BASE}.v
+	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" ${PREFIX}mode_template.v > ${TESTBENCH_BASE}.v
 ${TESTBENCH_BASE}.cpp: mode_template.cpp
-	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" mode_template.cpp > ${TESTBENCH_BASE}.cpp
+	sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" ${PREFIX}mode_template.cpp > ${TESTBENCH_BASE}.cpp

tests/write_read.cpp

@@ -30,7 +30,9 @@ int main(int argc, char **argv) {
 	sim->rdy = 1;
 	progress();
 
+#ifndef READ_ONLY
 	sim->data_ctrl = 0b110011011111001100011111;
+#endif
 	sim->activate = 1;
 
 	while (!sim->master_finished)
@@ -41,6 +43,7 @@ int main(int argc, char **argv) {
 	sim->rdy = 0;
 	progress_n(5);
 
+#ifndef READ_ONLY
 	sim->data_ctrl = 0xFE3456;
 	sim->activate = 1;
 	sim->ss = 1;
@@ -52,6 +55,7 @@ int main(int argc, char **argv) {
 	sim->ss = 0;
 	sim->rdy = 0;
 	progress_n(5);
+#endif
 
 	sim->final();
 	delete sim;