move tests

Makefile

@@ -1,19 +0,0 @@
-TESTBENCH_BASE=test_spi_write_read_mode0
-AUXFILES=spi_master.v spi_slave.v
-CPP_TESTBENCH=test_spi_write_read_mode0.cpp
-WAVEFILE=test_spi_write_read_mode0.vcd
-
-FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
-
-all: obj_dir/V${TESTBENCH_BASE}
-	./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
-
-obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
-	verilator -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
-obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
-	make -C obj_dir -f V${TESTBENCH_BASE}.mk
-
-run:
-	./obj_dir/V${TESTBENCH_CASE}
-clean:
-	$(RM) obj_dir/*

spi_master.v

@@ -1,3 +1,8 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
 module spi_master
 #(
 	parameter WID = 24, // Width of bits per transaction.

spi_slave.v

@@ -1,3 +1,8 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
 module spi_slave
 #(
 	parameter WID = 24, // Width of bits per transaction.

tests/mode00.cpp

@@ -0,0 +1,3 @@
+#include "Vmode00.h"
+using TopModule = Vmode00;
+#include "write_read.cpp"

tests/mode00.v

@@ -0,0 +1,34 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module mode00 (
+	input clk,
+	input [23:0] data_ctrl,
+	input activate,
+	input ss,
+	input rdy,
+	output master_finished
+);
+
+spi_write_read
+#(
+	.POLARITY(0),
+	.PHASE(0)
+) base (
+	.clk(clk),
+	.data_ctrl(data_ctrl),
+	.activate(activate),
+	.master_finished(master_finished),
+	.ss(ss),
+	.rdy(rdy)
+);
+
+initial begin
+	$dumpfile("mode00.vcd");
+	$dumpvars();
+end
+
+endmodule

tests/run.sh

@@ -0,0 +1,5 @@
+#!/bin/sh
+
+for i in 00; do
+	make -f run_mode.makefile MODE="$i"
+done

tests/run_mode.makefile

@@ -0,0 +1,25 @@
+# (c) Peter McGoron 2022
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v.2.0. If a copy of the MPL was not distributed with this
+# file, You can obtain one at https://mozilla.org/MPL/2.0/.
+
+TESTBENCH_BASE=mode${MODE}
+AUXFILES=../spi_master.v ../spi_slave.v
+
+CPP_TESTBENCH=${TESTBENCH_BASE}.cpp
+WAVEFILE=${TESTBENCH_BASE}.vcd
+
+FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
+
+all: obj_dir/V${TESTBENCH_BASE}
+	./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
+
+obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
+	verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
+obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
+	make -C obj_dir -f V${TESTBENCH_BASE}.mk
+
+run:
+	./obj_dir/V${TESTBENCH_CASE}
+clean:
+	$(RM) obj_dir/*

tests/spi_write_read.v

@@ -1,13 +1,21 @@
-module test_spi_write_read_mode0
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module spi_write_read
+#(
+	parameter POLARITY = 0,
+	parameter PHASE = 0
+)
 (
 	input clk,
 	input [23:0] data_ctrl,
 	input activate,
 	input ss,
 	input rdy,
-	output master_finished,
-	output slave_finished,
-	output slave_error
+	output master_finished
 );
 
 wire miso;
@@ -16,6 +24,8 @@ wire sck;
 wire ss_L = !ss;
 
 reg [23:0] from_slave_data;
+reg slave_finished;
+reg slave_error;
 
 spi_master master
 (
@@ -52,9 +62,4 @@ always @ (posedge clk) begin
 	end
 end
 
-initial begin
-	$dumpfile("test_spi_write_read_mode0.vcd");
-	$dumpvars();
-end
-
 endmodule

tests/write_read.cpp

@@ -1,7 +1,5 @@
 #include <stdio.h>
 #include <verilated.h>
-#include "Vtest_spi_write_read_mode0.h"
-using TopModule = Vtest_spi_write_read_mode0;
 
 VerilatedContext *ctx;
 TopModule *sim;