cleanup, add ready pin to slave
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10b9b756c6
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a879e31949
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@ -2,7 +2,7 @@ module spi_master
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#(
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter CYCLE_HALF_WAIT = 3, // Half of the wait time of a cycle
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parameter CYCLE_HALF_WAIT = 1, // Half of the wait time of a cycle
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parameter TIMER_LEN = 3, // Length in bits required to store CYCLE_HALF_WAIT
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parameter POLARITY = 0, // 0 = sck idle low, 1 = sck idle high
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parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
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30
spi_slave.v
30
spi_slave.v
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@ -18,6 +18,7 @@ module spi_slave
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output miso,
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`endif
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output finished,
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input rdy,
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output err
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);
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@ -25,6 +26,7 @@ wire ss = !ss_L;
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reg sck_delay = 0;
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reg [WID_LEN-1:0] bit_counter = 0;
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reg ss_delay = 0;
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reg ready_at_start = 0;
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`ifndef SPI_SLAVE_NO_WRITE
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reg [WID-1:0] send_buf = 0;
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@ -59,6 +61,14 @@ task setup_bits();
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end
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endtask
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task check_counter();
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if (bit_counter == WID) begin
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err <= ready_at_start;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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endtask
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always @ (posedge clk) begin
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sck_delay <= sck;
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ss_delay <= ss;
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@ -68,11 +78,12 @@ always @ (posedge clk) begin
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bit_counter <= 0;
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finished <= 0;
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err <= 0;
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ready_at_start <= rdy;
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setup_bits();
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end
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2'b10: begin // falling edge
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finished <= 1;
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finished <= ready_at_start;
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end
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2'b11: begin
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case ({sck_delay, sck})
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@ -84,11 +95,7 @@ always @ (posedge clk) begin
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end
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if (POLARITY == 0) begin
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if (bit_counter == WID) begin
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err <= 1;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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check_counter();
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end
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end
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2'b10: begin // falling edge
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@ -99,17 +106,16 @@ always @ (posedge clk) begin
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end
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if (POLARITY == 1) begin
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if (bit_counter == WID) begin
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err <= 1;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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check_counter();
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end
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end
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default: ;
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endcase
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end
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2'b00: ;
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2'b00: if (!rdy) begin
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finished <= 0;
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err <= 0;
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end
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endcase
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end
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@ -25,9 +25,11 @@ int main(int argc, char **argv) {
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sim->ss = 0;
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sim->clk = 0;
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sim->activate = 0;
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sim->rdy = 0;
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progress_n(8);
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sim->ss = 1;
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sim->rdy = 1;
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progress();
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sim->data_ctrl = 0b110011011111001100011111;
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@ -36,7 +38,21 @@ int main(int argc, char **argv) {
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while (!sim->master_finished)
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progress();
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progress_n(5);
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sim->activate = 0;
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sim->ss = 0;
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sim->rdy = 0;
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progress_n(5);
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sim->data_ctrl = 0xFE3456;
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sim->activate = 1;
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sim->ss = 1;
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sim->rdy = 1;
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while (!sim->master_finished)
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progress();
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progress_n(5);
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sim->activate = 0;
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sim->ss = 0;
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sim->rdy = 0;
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progress_n(5);
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sim->final();
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@ -4,6 +4,7 @@ module test_spi_write_read_mode0
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished,
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output slave_finished,
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output slave_error
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@ -31,7 +32,7 @@ spi_master master
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reg [23:0] data_from_master;
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reg [23:0] data_to_master = 24'b111011011100010101010101;
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spi_slave spi_slave
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spi_slave slave
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(
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.clk(clk),
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.sck(sck),
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@ -41,6 +42,7 @@ spi_slave spi_slave
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.mosi(mosi),
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.miso(miso),
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.finished(slave_finished),
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.rdy(rdy),
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.err(slave_error)
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);
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