145 lines
2.8 KiB
Verilog
145 lines
2.8 KiB
Verilog
module spi_master
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#(
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter CYCLE_HALF_WAIT = 1, // Half of the wait time of a cycle
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parameter TIMER_LEN = 3, // Length in bits required to store CYCLE_HALF_WAIT
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parameter POLARITY = 0, // 0 = sck idle low, 1 = sck idle high
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parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
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)
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(
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input clk,
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`ifndef SPI_MASTER_NO_READ
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output reg [WID-1:0] from_slave,
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input miso,
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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input [WID-1:0] to_slave,
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output mosi,
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`endif
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output sck_wire,
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output finished,
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input arm
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);
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parameter WAIT_ON_ARM = 0;
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parameter ON_CYCLE = 1;
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parameter CYCLE_WAIT = 2;
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parameter WAIT_FINISHED = 3;
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reg [1:0] state = WAIT_ON_ARM;
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reg [WID_LEN-1:0] bit_counter = 0;
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reg [TIMER_LEN-1:0] timer = 0;
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`ifndef SPI_MASTER_NO_WRITE
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reg [WID-1:0] send_buf = 0;
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`endif
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reg sck = 0;
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assign sck_wire = sck;
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task idle_state();
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if (POLARITY == 0) begin
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sck <= 0;
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end else begin
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sck <= 1;
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end
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`ifndef SPI_MASTER_NO_WRITE
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mosi <= 0;
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`endif
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timer <= 0;
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bit_counter <= 0;
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endtask
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task read_data();
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`ifndef SPI_MASTER_NO_READ
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from_slave <= from_slave << 1;
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from_slave[0] <= miso;
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`endif
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endtask
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task write_data();
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`ifndef SPI_MASTER_NO_WRITE
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mosi <= send_buf[WID-1];
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send_buf <= send_buf << 1;
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`endif
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endtask
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task setup_bits();
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/* at Mode 00, the transmission starts with
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* a rising edge, and at mode 11, it starts with a falling
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* edge. For both modes, these are READs.
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*
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* For mode 01 and mode 10, the first action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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mosi <= to_slave[WID-1];
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send_buf <= to_slave << 1;
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state <= CYCLE_WAIT;
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end else begin
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send_buf <= to_slave;
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state <= ON_CYCLE;
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end
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endtask
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always @ (posedge clk) begin
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case (state)
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WAIT_ON_ARM: begin
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if (!arm) begin
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idle_state();
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finished <= 0;
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end else begin
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setup_bits();
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end
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end
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ON_CYCLE: begin
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if (sck) begin // rising edge
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if (PHASE == 1) begin
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write_data();
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end else begin
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read_data();
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end
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if (POLARITY == 0) begin
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bit_counter <= bit_counter + 1;
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end
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end else begin // falling edge
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if (PHASE == 1) begin
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read_data();
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end else begin
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write_data();
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end
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if (POLARITY == 1) begin
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bit_counter <= bit_counter + 1;
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end
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end
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state <= CYCLE_WAIT;
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end
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CYCLE_WAIT: begin
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if (timer == CYCLE_HALF_WAIT) begin
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timer <= 0;
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// Stop transfer when the clock returns
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// to its original polarity.
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if (bit_counter == WID && sck == POLARITY) begin
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state <= WAIT_FINISHED;
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end else begin
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state <= ON_CYCLE;
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sck <= !sck;
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end
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end else begin
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timer <= timer + 1;
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end
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end
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WAIT_FINISHED: begin
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finished <= 1;
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idle_state();
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if (!arm) begin
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state <= WAIT_ON_ARM;
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end
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end
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endcase
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end
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endmodule
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