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Verilog SPI
4 Commits 1 Branch 2 Tags 132 KiB
Verilog 72.5%
Python 14.2%
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Peter McGoron a879e31949 cleanup, add ready pin to slave 2022-07-21 01:53:38 -04:00
Makefile mode 00, write from master to slave works 2022-07-21 01:09:45 -04:00
spi_master.v cleanup, add ready pin to slave 2022-07-21 01:53:38 -04:00
spi_slave.v cleanup, add ready pin to slave 2022-07-21 01:53:38 -04:00
test_spi_write_read_mode0.cpp cleanup, add ready pin to slave 2022-07-21 01:53:38 -04:00
test_spi_write_read_mode0.v cleanup, add ready pin to slave 2022-07-21 01:53:38 -04:00