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mode 00, write from slave to master works

This commit is contained in:
Peter McGoron 2022-07-21 01:29:39 -04:00
parent c4f401cff2
commit 10b9b756c6
2 changed files with 35 additions and 16 deletions
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34
spi_master.v
View File

@ -65,6 +65,23 @@ task write_data();
`endif
endtask
task setup_bits();
/* at Mode 00, the transmission starts with
* a rising edge, and at mode 11, it starts with a falling
* edge. For both modes, these are READs.
*
* For mode 01 and mode 10, the first action is a WRITE.
*/
if (POLARITY == PHASE) begin
mosi <= to_slave[WID-1];
send_buf <= to_slave << 1;
state <= CYCLE_WAIT;
end else begin
send_buf <= to_slave;
state <= ON_CYCLE;
end
endtask
always @ (posedge clk) begin
case (state)
WAIT_ON_ARM: begin
@ -72,22 +89,7 @@ always @ (posedge clk) begin
idle_state();
finished <= 0;
end else begin
/* at Mode 00, the transmission starts with
* a rising edge, and at mode 11, it starts
* with a falling edge. For both modes,
* these are READs.
*
* For mode 01 and mode 10, the first
* action is a WRITE.
*/
if (POLARITY == PHASE) begin
mosi <= to_slave[WID-1];
send_buf <= to_slave << 1;
state <= CYCLE_WAIT;
end else begin
send_buf <= to_slave;
state <= ON_CYCLE;
end
setup_bits();
end
end
ON_CYCLE: begin

17
spi_slave.v
View File

@ -44,6 +44,21 @@ task write_data();
`endif
endtask
task setup_bits();
/* at Mode 00, the transmission starts with
* a rising edge, and at mode 11, it starts with a falling
* edge. For both modes, these are READs.
*
* For mode 01 and mode 10, the first action is a WRITE.
*/
if (POLARITY == PHASE) begin
miso <= to_master[WID-1];
send_buf <= to_master << 1;
end else begin
send_buf <= to_master;
end
endtask
always @ (posedge clk) begin
sck_delay <= sck;
ss_delay <= ss;
@ -53,6 +68,8 @@ always @ (posedge clk) begin
bit_counter <= 0;
finished <= 0;
err <= 0;
setup_bits();
end
2'b10: begin // falling edge
finished <= 1;