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Verilog SPI
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Peter McGoron 10b9b756c6 mode 00, write from slave to master works 2022-07-21 01:29:39 -04:00
Makefile mode 00, write from master to slave works 2022-07-21 01:09:45 -04:00
spi_master.v mode 00, write from slave to master works 2022-07-21 01:29:39 -04:00
spi_slave.v mode 00, write from slave to master works 2022-07-21 01:29:39 -04:00
test_spi_write_read_mode0.cpp start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
test_spi_write_read_mode0.v start spi master and slave with testbench 2022-07-20 19:41:54 -04:00