58 lines
952 B
Verilog
58 lines
952 B
Verilog
/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module read_only_mode@MODE@ (
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input clk,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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wire miso;
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wire sck;
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wire ss_L = !ss;
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reg [23:0] from_slave_data;
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reg finished;
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reg err;
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spi_master_no_write
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#(
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.POLARITY(@POLARITY@),
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.PHASE(@PHASE@)
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) master (
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.clk(clk),
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.from_slave(from_slave_data),
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.miso(miso),
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.sck_wire(sck),
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.finished(master_finished),
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.arm(activate)
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);
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reg [23:0] to_master = 24'hF4325F;
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spi_slave_no_read
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#(
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.POLARITY(@POLARITY@),
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.PHASE(@PHASE@)
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) slave (
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.clk(clk),
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.sck(sck),
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.ss_L(ss_L),
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.to_master(to_master),
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.miso(miso),
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.finished(finished),
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.rdy(rdy),
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.err(finished)
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);
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initial begin
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$dumpfile("read_only_mode@MODE@.vcd");
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$dumpvars();
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end
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endmodule
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