46 lines
1.6 KiB
Markdown
46 lines
1.6 KiB
Markdown
# Verilog SPI
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Verilog SPI master and slave that supports all modes and variable width
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via parameters.
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## License
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All code in this project is licensed to the terms of the Mozilla Public
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License, v.2.0. A copy of this license may be found in the file `COPYING`. You
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can obtain one at https://mozilla.org/MPL/2.0/.
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All Verilog source in this project is dual-licensed under the MPL v2.0
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and the CERN-OHL-W v2.0 (or any later version).
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## Tests
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Run `./mk.sh` in `tests/` to generate and run tests.
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## Modules
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"master_no_read" and "slave_no_write" have no Master In, Slave Out ("miso")
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wires (and no corresponding shift registers), while "master_no_write"
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and "slave_no_read" have no Master Out, Slave In ("mosi") wires. This
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is for compatability for "SPI compatible" devices that are read only.
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"master_ss" and others include a timer that will assert the Slave Select
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pin and wait a set number of clock cycles before starting the SPI transfer.
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## SPI Modes
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Modes are denoted by `modePH`, where `P` is the polarity (0 for normal,
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1 for inverted) and `H` for phase:
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* `H = 0` means the device reads on a rising edge and writes on a falling
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edge.
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* `H = 1` means the device reads on a falling edge and writes on a rising
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edge.
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Although these modules support all SPI modes, they are labeled slightly
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differently from other SPI modes. The phase factor is denoted in terms
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of falling and rising edges, not in terms of leading and trailing edges.
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This means that polarity also flips the phase term, so a mode 3 device
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is a mode 10 device. Devices with regular clock polarity are unaffected,
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so a mode 0 device is a mode 00 device, and a mode 1 device is a mode
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01 device.
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