peter
/
spi
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Verilog SPI
31 Commits 1 Branch 2 Tags 132 KiB
Verilog 72.5%
Python 14.2%
C++ 13.1%
Shell 0.2%
Go to file
Peter McGoron bf78682e73 clean up tests 2024-01-23 14:05:26 -05:00
tests clean up tests 2024-01-23 14:05:26 -05:00
.gitignore clean up tests 2024-01-23 14:05:26 -05:00
COPYING add COPYING 2022-07-21 02:37:34 -04:00
COPYING_OHL rewrite entire test harness 2022-10-22 18:34:54 -04:00
README.md clean up tests 2024-01-23 14:05:26 -05:00
spi_master.v clean up tests 2024-01-23 14:05:26 -05:00
spi_master_ss.v clean up tests 2024-01-23 14:05:26 -05:00
spi_slave.v clean up tests 2024-01-23 14:05:26 -05:00

README.md

Verilog SPI

Verilog SPI master and slave that supports all modes and variable width via parameters.

License

All code in this project is licensed to the terms of the Mozilla Public License, v.2.0. A copy of this license may be found in the file COPYING. You can obtain one at https://mozilla.org/MPL/2.0/.

All Verilog source in this project is dual-licensed under the MPL v2.0 and the CERN-OHL-W v2.0.

Tests

Run ./mk.sh in tests/ to generate and run tests.

Modules

"master_ss" and others include a timer that will assert the Slave Select pin and wait a set number of clock cycles before starting the SPI transfer.

SPI Modes

Modes are denoted by modePH, where P is the polarity (0 for normal, 1 for inverted) and H for phase:

  • H = 0 means the device reads on a rising edge and writes on a falling edge.
  • H = 1 means the device reads on a falling edge and writes on a rising edge.

Although these modules support all SPI modes, they are labeled slightly differently from other SPI modes. The phase factor is denoted in terms of falling and rising edges, not in terms of leading and trailing edges. This means that polarity also flips the phase term, so a mode 3 device is a mode 10 device. Devices with regular clock polarity are unaffected, so a mode 0 device is a mode 00 device, and a mode 1 device is a mode 01 device.