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Verilog SPI
8 Commits 1 Branch 2 Tags 132 KiB
Verilog 72.5%
Python 14.2%
C++ 13.1%
Shell 0.2%
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Peter McGoron d8b011110a successfully test mode01, add Makefile 2022-07-21 03:01:58 -04:00
tests successfully test mode01, add Makefile 2022-07-21 03:01:58 -04:00
.gitignore add gitignore 2022-07-21 02:37:54 -04:00
COPYING add COPYING 2022-07-21 02:37:34 -04:00
spi_master.v move tests 2022-07-21 02:37:22 -04:00
spi_slave.v move tests 2022-07-21 02:37:22 -04:00