refactor control loop interface
This commit is contained in:
parent
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054609a459
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@ -17,5 +17,8 @@ Read `doc/copying/docker.md` to set up the Docker build environment.
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* `doc/`: Documentation.
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* `doc/copying`: Licenses.
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* `gateware/`: FPGA source.
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* `gateware/rtl`: Verilog sources.
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* `gateware/rtl/control_loop`: Control loop code.
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* `gateware/rtl/spi`: SPI code.
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* `linux/`: Software that runs on the controller.
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* `opensbi/`: OpenSBI configuration files and source fragments.
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@ -7,9 +7,7 @@ source distribution.
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__________________________________________________________________________
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This manual describes the controller software programming. This guide does not
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describe client programming (programs that run on the client and interface with
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the controller). It does not describe Verilog: see `verilog_manual.md` for
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that.
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describe Verilog: see `verilog_manual.md` for that.
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# Preqreuisites
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@ -0,0 +1,220 @@
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import textwrap
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class Descr:
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def __init__(self, name, blen, rwperm, num, descr):
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"""
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:param name: Name of the pin without numerical suffix.
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:param blen: Bit length of the pin.
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:param doc: Restructured text documentation of the register.
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:param num: The amount of registers of the same type.
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:param read_only: A string that must be either "read-only" or "write-write".
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"""
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self.name = name
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self.blen = blen
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self.doc = textwrap.deindent(descr)
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self.num =num
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self.read_only = read_only == "read-only"
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@classmethod
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def from_dict(cls, jsdict, name):
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return cls(name, jsdict[name]["len"], jsdict[name]["ro"], jsdict[name]["num"], jsdict[name]["doc"])
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def store_to_dict(self, d):
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d[self.name = {
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"len": self.blen,
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"doc": self.doc,
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"num": self.num,
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"ro": ro
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}
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registers = [
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Descr("adc_sel", 3, "read-write", """\
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Select which on-FPGA SPI master controls the ADC.
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Valid settings:
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* ``0``: ADC is controlled by MMIO registers.
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* ``0b10``: ADC is controlled by MMIO registers, but conversion is
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disabled. This is used to flush output from an out-of-sync ADC.
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* ``0b100``: ADC 0 only. ADC is controlled by control loop."""),
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Descr("adc_finished", "read-only", """\
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Signals that an ADC master has finished an SPI cycle.
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Values:
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* ``0``: MMIO master is either not armed or currently in a
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SPI transfer.
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* ``1``: MMIO master has finished.
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This flag is on only when ``adc_arm`` is high. The flag does not
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mean that data has been received successfully, only that the master
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has finished it's SPI transfer.
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"""),
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Descr("adc_arm", "read-write", """\
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Start a DAC master SPI transfer.
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If ``adc_arm`` is raised from and the master is currently not in a SPI
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transfer, the SPI master will start an SPI transfer and write data
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into ``adc_recv_buf``.
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If ``adc_arm`` is raised while the master is in an SPI transfer,
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nothing changes.
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If ``adc_arm`` is lowered while the master is in an SPI transfer,
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nothing changes. The SPI cycle will continue to execute and it will
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continue to write data to ``adc_recv_buf``.
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If the SPI transfer finishes and ``adc_arm`` is still set to
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1, then ``adc_finished`` is raised to 1. If ``adc_arm`` is lowered
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in this state, then ``adc_finished`` is lowered.
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Linear Technologies ADCs must not have their SPI transfers
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interrupted. The transfer can be interrupted by
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1. Interrupt the signal physically (i.e. pulling out cable connecting
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the FPGA to the ADC)
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2. Reset of the ADC master
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3. Reset of the FPGA
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4. Switching ``adc_sel`` to the control loop
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If the ADC is interrupted then it will be in an unknown transfer
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state. To recover from an unknown transfer state, set ``adc_sel``
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to ``0b10`` and run a SPI transfer cycle. This will run the SPI
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clock and flush the ADC buffer. The only other way is to power-cycle
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the ADC.
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If ``adc_sel`` is not set to 0 then the transfer will proceed
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as normal, but no data will be received from the ADC."""),
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Descr("adc_recv_buf", "read-only", """\
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ADC Master receive buffer.
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This buffer is stable if there is no ADC transfer caused by ``adc_arm``
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is in process.
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This register only changes if an SPI transfer is triggered by the MMIO
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_sel", 2, "read-write", """\
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Select which on-FPGA SPI master controls the DAC.
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Valid settings:
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* ``0``: DAC is controlled by MMIO registers.
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* ``0b10``: DAC 0 only. DAC is controlled by control loop."""),
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Descr("dac_finished", 1, "read-only", """\
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Signals that the DAC master has finished transmitting data.
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Values:
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* ``0``: MMIO master is either not armed or currently in a
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SPI transfer.
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* ``1``: MMIO master has finished transmitting.
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This flag is on only when ``dac_arm`` is high. The flag does not
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mean that data has been received or transmitted successfully, only that
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the master has finished it's SPI transfer."""),
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Descr("dac_arm", 1, "read-write", """\
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Start a DAC master SPI transfer.
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If ``dac_arm`` is raised from and the master is currently not in a SPI
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transfer, the SPI master reads from the ``dac_send_buf`` register and sends
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it over the wire to the DAC, while reading data from the DAC into
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``dac_recv_buf``.
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If ``dac_arm`` is raised while the master is in an SPI transfer,
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nothing changes.
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If ``dac_arm`` is lowered while the master is in an SPI transfer,
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nothing changes. The SPI cycle will continue to execute and it will
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continue to write data to ``dac_recv_buf``.
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If the SPI transfer finishes and ``dac_arm`` is still set to
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1, then ``dac_finished`` is raised to 1. If ``dac_arm`` is lowered
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in this state, then ``dac_finished`` is lowered.
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Analog Devices DACs can have their SPI transfers interrupted without
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issue. However it is currently not possible to interrupt SPI transfers
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in software without resetting the entire device.
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If ``dac_sel`` is set to another master then the transfer will proceed
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as normal, but no data will be sent to or received from the DAC."""),
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Descr("dac_recv_buf", 24, "read-only", """\
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DAC master receive buffer.
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This buffer is stable if there is no DAC transfer caused by ``dac_arm``
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is in process.
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This register only changes if an SPI transfer is triggered by the MMIO
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_send_buf, 24, "read-write", """\
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DAC master send buffer.
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Fill this buffer with a 24 bit Analog Devices DAC command. Updating
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this buffer does not start an SPI transfer. To send data to the DAC,
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fill this buffer and raise ``dac_arm``.
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The DAC copies this buffer into an internal register when writing data.
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Modifying this buffer during a transfer does not disrupt an in-process
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transfer."""),
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Descr("cl_assert_change", 1, "read-write", """\
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Flush parameter changes to control loop.
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When this bit is raised from low to high, this signals the control
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loop that it should read in new values from the MMIO registers.
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While the bit is raised high, the control loop will read the constants
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at most once.
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When this bit is raised from high to low before ``cl_change_made``
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is asserted by the control loop, nothing happens."""),
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Descr("cl_change_made", 1, "read-only", """\
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Signal from the control loop that the parameters have been applied.
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This signal goes high only while ``cl_assert_change`` is high. No
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change will be applied afterwards while both are high."""),
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Descr("cl_in_loop_in", 1, "read-only", """\
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This bit is high if the control loop is running."""),
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Descr("cl_setpt_in", 18, "read-write", """\
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Setpoint of the control loop.
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This is a twos-complement number in ADC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_P_in", 64, "read-write", """\
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Proportional parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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bits and 43 fractional bits. This is applied to the error
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_I_in", 64, "read-write", """\
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Integral parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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bits and 43 fractional bits. This is applied to the error
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_delay_in", 16, "read-write", """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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the loop should wait between loop executions.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_cycle_count", 18, "read-only", """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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the loop should wait between loop executions."""),
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Descr("cl_z_pos", 20, "read-only", """\
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Control loop DAC Z position.
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"""),
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Descr("cl_z_measured", 18, "read-only", """\
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Control loop ADC Z position.
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"""),
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]
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@ -1,7 +1,6 @@
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m4_changequote(`⟨', `⟩')
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m4_changecom(⟨/*⟩, ⟨*/⟩)
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m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩)
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m4_include(../control_loop/control_loop_cmds.m4)
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/*
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Copyright 2023 (C) Peter McGoron
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@ -291,14 +290,18 @@ m4_define(CL_DATA_WID, CL_CONSTS_WID)
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m4_adc_wires(ADC_TYPE3_WID, 6, ADC_PORTS),
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m4_adc_wires(ADC_TYPE3_WID, 7, ADC_PORTS),
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output cl_in_loop,
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input [M4_CONTROL_LOOP_CMD_WIDTH-1:0] cl_cmd,
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input [CL_DATA_WID-1:0] cl_word_in,
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output reg [CL_DATA_WID-1:0] cl_word_out,
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input cl_start_cmd,
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output cl_finish_cmd,
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input cl_assert_change,
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output cl_change_made,
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output [DAC_DATA_WID-1:0] cl_z_report
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input cl_run_loop_in,
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input [ADC_TYPE1_WID-1:0] cl_setpt_in,
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input [CL_DATA_WID-1:0] cl_P_in,
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input [CL_DATA_WID-1:0] cl_I_in,
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input [CL_DELAY_WID-1:0] cl_delay_in,
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output [CYCLE_COUNT_WID-1:0] cl_cycle_count,
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output [DAC_DATA_WID-1:0] cl_z_pos,
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output [ADC_WID-1:0] cl_z_measured
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);
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assign set_low = 0;
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@ -377,12 +380,16 @@ control_loop #(
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.adc_miso(adc_sdo_port_0[2]),
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.adc_conv_L(adc_conv_L_port_0[2]),
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.adc_sck(adc_sck_port_0[2]),
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.cmd(cl_cmd),
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.word_in(cl_word_in),
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.word_out(cl_word_out),
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.start_cmd(cl_start_cmd),
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.finish_cmd(cl_finish_cmd),
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.z_report(cl_z_report)
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.assert_change(cl_assert_change),
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.change_made(cl_change_made),
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.run_loop_in(cl_run_loop_in),
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.setpt_in(cl_setpt_in),
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.P_in(cl_P_in),
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.I_in(cl_I_in),
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.delay_in(cl_delay_in),
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.cycle_count(cl_cycle_count),
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.z_pos(cl_z_pos),
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.z_measured(cl_z_measured)
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);
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endmodule
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@ -38,7 +38,7 @@ obj_dir/Vcontrol_loop_sim_top.mk: control_loop_sim.cpp ${COMMON} \
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../spi/spi_master_ss.v \
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../spi/spi_slave_no_write.v \
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control_loop_sim_top.v control_loop_sim_top.v \
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control_loop_cmds.vh control_loop.v \
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control_loop.v \
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${control_loop_math_verilog}
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verilator --cc --exe -Wall --trace --trace-fst \
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--top-module control_loop_sim_top \
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@ -48,19 +48,13 @@ obj_dir/Vcontrol_loop_sim_top.mk: control_loop_sim.cpp ${COMMON} \
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control_loop_sim_top.v control_loop.v control_loop_sim.cpp \
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${COMMON_CPP} adc_sim.v dac_sim.v ../spi/spi_master_ss.v \
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../spi/spi_slave_no_read.v ../spi/spi_slave.v
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obj_dir/Vcontrol_loop_sim_top: obj_dir/Vcontrol_loop_sim_top.mk control_loop_cmds.h
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obj_dir/Vcontrol_loop_sim_top: obj_dir/Vcontrol_loop_sim_top.mk
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cd obj_dir && make -f Vcontrol_loop_sim_top.mk
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####### Codegen ########
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include ../common.makefile
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CODEGEN_FILES=control_loop_cmds.h boothmul_preprocessed.v control_loop_math.v control_loop.v control_loop_cmds.vh
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CODEGEN_FILES=boothmul_preprocessed.v control_loop_math.v control_loop.v
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codegen: ${CODEGEN_FILES}
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control_loop_cmds.vh: control_loop_cmds.m4
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m4 -P control_loop_cmds.vh.m4 > control_loop_cmds.vh
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control_loop_cmds.h: control_loop_cmds.m4
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echo '#pragma once' > control_loop_cmds.h
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m4 -P control_loop_cmds.h.m4 >> control_loop_cmds.h
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clean:
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rm -rf obj_dir *.fst ${CODEGEN_FILES}
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@ -27,7 +27,6 @@ module control_loop
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parameter CONSTS_SIZ = 7,
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m4_define(M4_CONSTS_WID, (CONSTS_WHOLE + CONSTS_FRAC))
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parameter DELAY_WID = 16,
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m4_define(M4_DATA_WID, M4_CONSTS_WID)
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parameter READ_DAC_DELAY = 5,
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parameter CYCLE_COUNT_WID = 18,
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parameter DAC_WID = 24,
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@ -47,7 +46,6 @@ m4_define(M4_E_WID, (DAC_DATA_WID + 1))
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) (
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input clk,
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input rst_L,
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output in_loop,
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output dac_mosi,
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input dac_miso,
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@ -58,14 +56,20 @@ m4_define(M4_E_WID, (DAC_DATA_WID + 1))
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output adc_conv_L,
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output adc_sck,
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/* Hacky ad-hoc read-write interface. */
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input [M4_CONTROL_LOOP_CMD_WIDTH-1:0] cmd,
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input [M4_DATA_WID-1:0] word_in,
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output reg [M4_DATA_WID-1:0] word_out,
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input start_cmd,
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output reg finish_cmd,
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output in_loop,
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output [DAC_DATA_WID-1:0] z_report
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input assert_change,
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output reg change_made,
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input run_loop_in,
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input [ADC_WID-1:0] setpt_in,
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input [M4_CONSTS_WID-1:0] P_in,
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input [M4_CONSTS_WID-1:0] I_in,
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input [DELAY_WID-1:0] delay_in,
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output [CYCLE_COUNT_WID-1:0] cycle_count,
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output [DAC_DATA_WID-1:0] z_pos,
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output [ADC_WID-1:0] z_measured
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);
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/************ ADC and DAC modules ***************/
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@ -104,6 +108,7 @@ spi_master_ss #(
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reg adc_arm;
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reg adc_finished;
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wire [ADC_WID-1:0] measured_value;
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assign z_measured = measured_value;
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wire adc_ready_to_arm_unused;
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localparam [3-1:0] DAC_REGISTER = 3'b001;
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@ -133,33 +138,30 @@ spi_master_ss_no_write #(
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* Parameters can be adjusted on the fly by the user. The modifications
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* cannot happen during a calculation, but calculations occur in a matter
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* of milliseconds. Instead, modifications are checked and applied at the
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* start of each iteration (CYCLE_START). Before this, the new values
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* have to be buffered.
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* start of each iteration (CYCLE_START).
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*/
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/* Setpoint: what should the ADC read */
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reg signed [ADC_WID-1:0] setpt = 0;
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reg signed [ADC_WID-1:0] setpt_buffer = 0;
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/* Integral parameter */
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reg signed [M4_CONSTS_WID-1:0] cl_I_reg = 0;
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reg signed [M4_CONSTS_WID-1:0] cl_I_reg_buffer = 0;
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/* Proportional parameter */
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reg signed [M4_CONSTS_WID-1:0] cl_p_reg = 0;
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reg signed [M4_CONSTS_WID-1:0] cl_p_reg_buffer = 0;
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/* Delay parameter (to make the loop run slower) */
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reg [DELAY_WID-1:0] dely = 0;
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reg [DELAY_WID-1:0] dely_buffer = 0;
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/************ Loop Control and Internal Parameters *************/
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reg running = 0;
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reg signed [DAC_DATA_WID-1:0] stored_dac_val = 0;
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assign z_report = stored_dac_val;
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assign z_pos = stored_dac_val;
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reg [CYCLE_COUNT_WID-1:0] last_timer = 0;
|
||||
assign cycle_count = last_timer;
|
||||
reg [CYCLE_COUNT_WID-1:0] counting_timer = 0;
|
||||
reg [M4_CONSTS_WID-1:0] adjval_prev = 0;
|
||||
|
||||
|
|
@ -214,12 +216,6 @@ control_loop_math #(
|
|||
* ┃ ↓
|
||||
* ┗━━━━━━━┛
|
||||
****** Outline
|
||||
* There are two systems: the read-write interface and the loop.
|
||||
* The read-write interface allows another module (i.e. the CPU)
|
||||
* to access and change constants. When a constant is changed the
|
||||
* loop must reset the values that are preserved between loops
|
||||
* (previous adjustment and previous delay).
|
||||
*
|
||||
* When the loop starts it must find the current value from the
|
||||
* DAC and write to it. The value from the DAC is then adjusted
|
||||
* with the output of the control loop. Afterwards it does not
|
||||
|
|
@ -253,125 +249,48 @@ always @ (posedge clk) begin
|
|||
end
|
||||
end
|
||||
|
||||
/**** Read-Write control interface.
|
||||
* `write_control` ensures that writes to the dirty bit do not happen when
|
||||
* the main loop is clearing the dirty bit.
|
||||
*/
|
||||
|
||||
wire write_control = state == WAIT_ON_DAC || !running;
|
||||
reg dirty_bit = 0;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (!rst_L) begin
|
||||
dirty_bit <= 0;
|
||||
finish_cmd <= 0;
|
||||
word_out <= 0;
|
||||
end else if (start_cmd && !finish_cmd) begin
|
||||
case (cmd)
|
||||
M4_CONTROL_LOOP_NOOP:
|
||||
finish_cmd <= 1;
|
||||
M4_CONTROL_LOOP_NOOP | M4_CONTROL_LOOP_WRITE_BIT:
|
||||
finish_cmd <= 1;
|
||||
M4_CONTROL_LOOP_STATUS: begin
|
||||
word_out[M4_DATA_WID-1:1] <= 0;
|
||||
word_out[0] <= running;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_STATUS | M4_CONTROL_LOOP_WRITE_BIT:
|
||||
if (write_control) begin
|
||||
running <= word_in[0];
|
||||
finish_cmd <= 1;
|
||||
dirty_bit <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_SETPT: begin
|
||||
word_out[M4_DATA_WID-1:ADC_WID] <= 0;
|
||||
word_out[ADC_WID-1:0] <= setpt;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_SETPT | M4_CONTROL_LOOP_WRITE_BIT:
|
||||
if (write_control) begin
|
||||
setpt_buffer <= word_in[ADC_WID-1:0];
|
||||
finish_cmd <= 1;
|
||||
dirty_bit <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_P: begin
|
||||
word_out <= cl_p_reg;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_P | M4_CONTROL_LOOP_WRITE_BIT: begin
|
||||
if (write_control) begin
|
||||
cl_p_reg_buffer <= word_in;
|
||||
finish_cmd <= 1;
|
||||
dirty_bit <= 1;
|
||||
end
|
||||
end
|
||||
M4_CONTROL_LOOP_I: begin
|
||||
word_out <= cl_I_reg;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_I | M4_CONTROL_LOOP_WRITE_BIT: begin
|
||||
if (write_control) begin
|
||||
cl_I_reg_buffer <= word_in;
|
||||
finish_cmd <= 1;
|
||||
dirty_bit <= 1;
|
||||
end
|
||||
end
|
||||
M4_CONTROL_LOOP_DELAY: begin
|
||||
word_out[M4_DATA_WID-1:DELAY_WID] <= 0;
|
||||
word_out[DELAY_WID-1:0] <= dely;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_DELAY | M4_CONTROL_LOOP_WRITE_BIT: begin
|
||||
if (write_control) begin
|
||||
dely_buffer <= word_in[DELAY_WID-1:0];
|
||||
finish_cmd <= 1;
|
||||
dirty_bit <= 1;
|
||||
end
|
||||
end
|
||||
M4_CONTROL_LOOP_ERR: begin
|
||||
word_out[M4_DATA_WID-1:M4_E_WID] <= 0;
|
||||
word_out[M4_E_WID-1:0] <= err_prev;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_Z: begin
|
||||
word_out[M4_DATA_WID-1:DAC_DATA_WID] <= 0;
|
||||
word_out[DAC_DATA_WID-1:0] <= stored_dac_val;
|
||||
finish_cmd <= 1;
|
||||
end
|
||||
M4_CONTROL_LOOP_CYCLES: begin
|
||||
word_out[M4_DATA_WID-1:CYCLE_COUNT_WID] <= 0;
|
||||
word_out[CYCLE_COUNT_WID-1:0] <= last_timer;
|
||||
finish_cmd <= 0;
|
||||
end
|
||||
endcase
|
||||
end else if (!start_cmd) begin
|
||||
finish_cmd <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign in_loop = state != INIT_READ_FROM_DAC || running;
|
||||
|
||||
/* Reset the change acknowledge interface after the master
|
||||
* stops its transfer.
|
||||
*
|
||||
* The module only writes to change_made in the main always block
|
||||
* when state == CYCLE_START, so make sure that this does not
|
||||
* compete with CYCLE_START.
|
||||
*/
|
||||
always @ (posedge clk) begin
|
||||
if (state != CYCLE_START && !assert_change && change_made)
|
||||
change_made <= 0;
|
||||
end
|
||||
|
||||
task reset_loop();
|
||||
to_dac <= 0;
|
||||
dac_arm <= 0;
|
||||
state <= INIT_READ_FROM_DAC;
|
||||
timer <= 0;
|
||||
stored_dac_val <= 0;
|
||||
setpt <= 0;
|
||||
dely <= 0;
|
||||
cl_I_reg <= 0;
|
||||
adjval_prev <= 0;
|
||||
err_prev <= 0;
|
||||
|
||||
adc_arm <= 0;
|
||||
arm_math <= 0;
|
||||
endtask
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (!rst_L) begin
|
||||
to_dac <= 0;
|
||||
dac_arm <= 0;
|
||||
state <= INIT_READ_FROM_DAC;
|
||||
timer <= 0;
|
||||
stored_dac_val <= 0;
|
||||
setpt <= 0;
|
||||
dely <= 0;
|
||||
cl_I_reg <= 0;
|
||||
adjval_prev <= 0;
|
||||
err_prev <= 0;
|
||||
|
||||
adc_arm <= 0;
|
||||
arm_math <= 0;
|
||||
reset_loop();
|
||||
end else case (state)
|
||||
INIT_READ_FROM_DAC: begin
|
||||
if (running) begin
|
||||
if (run_loop_in) begin
|
||||
running <= 1;
|
||||
to_dac <= {1'b1, DAC_REGISTER, 20'b0};
|
||||
dac_arm <= 1;
|
||||
state <= WAIT_FOR_DAC_READ;
|
||||
end else begin
|
||||
reset_loop();
|
||||
end
|
||||
end
|
||||
WAIT_FOR_DAC_READ: begin
|
||||
|
|
@ -396,21 +315,21 @@ always @ (posedge clk) begin
|
|||
end
|
||||
end
|
||||
CYCLE_START: begin
|
||||
if (!running) begin
|
||||
state <= INIT_READ_FROM_DAC;
|
||||
if (!run_loop_in) begin
|
||||
reset_loop();
|
||||
end else if (timer < dely) begin
|
||||
timer <= timer + 1;
|
||||
end else begin
|
||||
/* On change of constants, previous values are invalidated. */
|
||||
if (dirty_bit) begin
|
||||
setpt <= setpt_buffer;
|
||||
dely <= dely_buffer;
|
||||
cl_I_reg <= cl_I_reg_buffer;
|
||||
cl_p_reg <= cl_p_reg_buffer;
|
||||
if (assert_change && !change_made) begin
|
||||
change_made <= 1;
|
||||
|
||||
setpt <= setpt_in;
|
||||
dely <= delay_in;
|
||||
cl_I_reg <= I_in;
|
||||
cl_p_reg <= P_in;
|
||||
adjval_prev <= 0;
|
||||
err_prev <= 0;
|
||||
|
||||
dirty_bit <= 0;
|
||||
end
|
||||
|
||||
state <= WAIT_ON_ADC;
|
||||
|
|
|
|||
|
|
@ -1,7 +0,0 @@
|
|||
m4_changequote(`⟨', `⟩')m4_dnl
|
||||
m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl
|
||||
m4_define(generate_macro, ⟨m4_dnl
|
||||
#define $1 $2 m4_dnl
|
||||
m4_define(M4_$1, $2)m4_dnl
|
||||
⟩)m4_dnl
|
||||
m4_include(control_loop_cmds.m4)
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
generate_macro(CONTROL_LOOP_NOOP, 0)
|
||||
generate_macro(CONTROL_LOOP_STATUS, 1)
|
||||
generate_macro(CONTROL_LOOP_SETPT, 2)
|
||||
generate_macro(CONTROL_LOOP_P, 3)
|
||||
generate_macro(CONTROL_LOOP_I, 4)
|
||||
generate_macro(CONTROL_LOOP_ERR, 5)
|
||||
generate_macro(CONTROL_LOOP_Z, 6)
|
||||
generate_macro(CONTROL_LOOP_CYCLES, 7)
|
||||
generate_macro(CONTROL_LOOP_DELAY, 8)
|
||||
generate_macro(CONTROL_LOOP_CMD_WIDTH, 8)
|
||||
generate_macro(CONTROL_LOOP_WRITE_BIT, (1 << (M4_CONTROL_LOOP_CMD_WIDTH-1)))
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
m4_changequote(`⟨', `⟩')m4_dnl
|
||||
m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl
|
||||
m4_define(generate_macro, ⟨m4_dnl
|
||||
`define $1 $2 m4_dnl
|
||||
m4_define(M4_$1, $2)m4_dnl
|
||||
⟩)m4_dnl
|
||||
m4_include(control_loop_cmds.m4)
|
||||
|
|
@ -14,7 +14,6 @@
|
|||
|
||||
#include <verilated.h>
|
||||
#include "control_loop_math_implementation.h"
|
||||
#include "control_loop_cmds.h"
|
||||
#include "Vcontrol_loop_sim_top.h"
|
||||
using ModType = Vcontrol_loop_sim_top;
|
||||
|
||||
|
|
@ -41,32 +40,27 @@ static void init(int argc, char **argv) {
|
|||
mod->rst_L = 1;
|
||||
}
|
||||
|
||||
static void set_value(V val, unsigned name) {
|
||||
mod->cmd = CONTROL_LOOP_WRITE_BIT | name;
|
||||
mod->word_into_loop = val;
|
||||
mod->start_cmd = 1;
|
||||
|
||||
do { run_clock(); } while (!mod->finish_cmd);
|
||||
mod->start_cmd = 0;
|
||||
run_clock();
|
||||
}
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
printf("sim top\n");
|
||||
init(argc, argv);
|
||||
Transfer func = Transfer{150, 0, 2, 1.1, 10, -1};
|
||||
|
||||
set_value(0b11010111000010100011110101110000101000111, CONTROL_LOOP_P);
|
||||
/* Constant values must be sized to 64 bits, or else the compiler
|
||||
* will think they are 32 bit and silently mess things up
|
||||
*/
|
||||
set_value((V)6 << CONSTS_FRAC, CONTROL_LOOP_I);
|
||||
set_value(20, CONTROL_LOOP_DELAY);
|
||||
set_value(10000, CONTROL_LOOP_SETPT);
|
||||
set_value(1, CONTROL_LOOP_STATUS);
|
||||
mod->P_in = 0b11010111000010100011110101110000101000111;
|
||||
mod->I_in = (V)6 << CONSTS_FRAC;
|
||||
mod->delay_in = 20;
|
||||
mod->setpt_in = 10000;
|
||||
mod->assert_change = 1;
|
||||
mod->run_loop_in = 1;
|
||||
mod->curset = 0;
|
||||
|
||||
for (int tick = 0; tick < 1000;) {
|
||||
if (mod->change_made) {
|
||||
mod->assert_change = 0;
|
||||
}
|
||||
|
||||
run_clock();
|
||||
if (mod->request && !mod->fulfilled) {
|
||||
/* Verilator values are not sign-extended to the
|
||||
|
|
@ -81,10 +75,6 @@ int main(int argc, char **argv) {
|
|||
mod->fulfilled = 0;
|
||||
tick++;
|
||||
}
|
||||
|
||||
if (mod->finish_cmd) {
|
||||
mod->start_cmd = 0;
|
||||
}
|
||||
}
|
||||
|
||||
mod->final();
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`include "control_loop_cmds.vh"
|
||||
|
||||
module control_loop_sim_top #(
|
||||
parameter ADC_WID = 18,
|
||||
|
|
@ -16,6 +15,7 @@ module control_loop_sim_top #(
|
|||
parameter DAC_DATA_WID = 20,
|
||||
parameter DAC_WID = 24,
|
||||
parameter DAC_WID_SIZ = 5,
|
||||
parameter CYCLE_COUNT_WID = 18,
|
||||
|
||||
parameter CONSTS_WHOLE = 21,
|
||||
parameter CONSTS_FRAC = 43,
|
||||
|
|
@ -35,11 +35,18 @@ module control_loop_sim_top #(
|
|||
input fulfilled,
|
||||
output adc_err,
|
||||
|
||||
input [`CONSTS_WID-1:0] word_into_loop,
|
||||
output [`CONSTS_WID-1:0] word_outof_loop,
|
||||
input start_cmd,
|
||||
output finish_cmd,
|
||||
input [`CONTROL_LOOP_CMD_WIDTH-1:0] cmd
|
||||
input assert_change,
|
||||
output change_made,
|
||||
|
||||
input run_loop_in,
|
||||
input [ADC_WID-1:0] setpt_in,
|
||||
input [`CONSTS_WID-1:0] P_in,
|
||||
input [`CONSTS_WID-1:0] I_in,
|
||||
input [DELAY_WID-1:0] delay_in,
|
||||
|
||||
output [CYCLE_COUNT_WID-1:0] cycle_count,
|
||||
output [DAC_DATA_WID-1:0] z_pos,
|
||||
output [ADC_WID-1:0] z_measured
|
||||
);
|
||||
|
||||
/* Emulate a control loop environment with simulator controlled
|
||||
|
|
@ -101,6 +108,7 @@ control_loop #(
|
|||
/* Keeping cycle half wait and conv wait the same
|
||||
* since it doesn't matter for this simulation */
|
||||
|
||||
.CYCLE_COUNT_WID(CYCLE_COUNT_WID),
|
||||
.CONSTS_WHOLE(CONSTS_WHOLE),
|
||||
.CONSTS_FRAC(CONSTS_FRAC),
|
||||
.CONSTS_SIZ(CONSTS_SIZ),
|
||||
|
|
@ -124,11 +132,18 @@ control_loop #(
|
|||
.adc_conv_L(adc_ss_L),
|
||||
.adc_sck(adc_sck),
|
||||
|
||||
.word_in(word_into_loop),
|
||||
.word_out(word_outof_loop),
|
||||
.start_cmd(start_cmd),
|
||||
.finish_cmd(finish_cmd),
|
||||
.cmd(cmd)
|
||||
.assert_change(assert_change),
|
||||
.change_made(change_made),
|
||||
|
||||
.run_loop_in(run_loop_in),
|
||||
.setpt_in(setpt_in),
|
||||
.P_in(P_in),
|
||||
.I_in(I_in),
|
||||
.delay_in(delay_in),
|
||||
|
||||
.cycle_count(cycle_count),
|
||||
.z_pos(z_pos),
|
||||
.z_measured(z_measured)
|
||||
);
|
||||
|
||||
`ifdef VERILATOR
|
||||
|
|
|
|||
|
|
@ -56,6 +56,8 @@ from litedram.modules import MT41K128M16
|
|||
from litedram.frontend.dma import LiteDRAMDMAReader
|
||||
from liteeth.phy.mii import LiteEthPHYMII
|
||||
|
||||
import mmio_descr
|
||||
|
||||
"""
|
||||
Keep this diagram up to date! This is the wiring diagram from the ADC to
|
||||
the named Verilog pins.
|
||||
|
|
@ -128,28 +130,26 @@ class Base(Module, AutoCSR):
|
|||
keyword arguments to pass all the arguments.
|
||||
"""
|
||||
|
||||
def _make_csr(self, name, csrclass, csrlen, description, num=None):
|
||||
""" Add a CSR for a pin `f"{name}_{num}"` with CSR type
|
||||
`csrclass`. This will automatically handle the `i_` and
|
||||
`o_` prefix in the keyword arguments.
|
||||
def _make_csr(self, reg, num=None):
|
||||
""" Add a CSR for a pin `f"{name}_{num}".`
|
||||
|
||||
This function is used to automate the creation of memory mapped
|
||||
IO pins for all the converters on the device.
|
||||
|
||||
`csrclass` must be CSRStorage (Read-Write) or CSRStatus (Read only).
|
||||
`csrlen` is the length in bits of the MMIO register. LiteX automatically
|
||||
takes care of byte alignment, etc. so the length can be any positive
|
||||
number.
|
||||
|
||||
Description is optional but recommended for debugging.
|
||||
:param name: Name of the MMIO register without prefixes or numerical
|
||||
suffix.
|
||||
:param num: Numerical suffix of this MMIO register. This is the only
|
||||
parameter that should change when adding multiple CSRs of the same
|
||||
name.
|
||||
"""
|
||||
|
||||
if name not in self.csrdict.keys():
|
||||
self.csrdict[name] = csrlen
|
||||
name = reg.name
|
||||
if num is not None:
|
||||
name = f"{name}_{num}"
|
||||
|
||||
csr = csrclass(csrlen, name=name, description=description)
|
||||
if self.ro == "read-only":
|
||||
csrclass = CSRStatus
|
||||
else:
|
||||
csrclass = CSRStorage
|
||||
|
||||
csr = csrclass(reg.blen, name=name, description=None)
|
||||
setattr(self, name, csr)
|
||||
|
||||
if csrclass is CSRStorage:
|
||||
|
|
@ -161,44 +161,13 @@ class Base(Module, AutoCSR):
|
|||
|
||||
def __init__(self, clk, sdram, platform):
|
||||
self.kwargs = {}
|
||||
self.csrdict = {}
|
||||
|
||||
for i in range(0,8):
|
||||
self._make_csr("adc_sel", CSRStorage, 3, f"Select ADC {i} Output", num=i)
|
||||
self._make_csr("dac_sel", CSRStorage, 3, f"Select DAC {i} Output", num=i)
|
||||
self._make_csr("dac_finished", CSRStatus, 1, f"DAC {i} Transmission Finished Flag", num=i)
|
||||
self._make_csr("dac_arm", CSRStorage, 1, f"DAC {i} Arm Flag", num=i)
|
||||
self._make_csr("dac_recv_buf", CSRStatus, 24, f"DAC {i} Received Data", num=i)
|
||||
self._make_csr("dac_send_buf", CSRStorage, 24, f"DAC {i} Data to Send", num=i)
|
||||
# self._make_csr("wf_arm", CSRStorage, 1, f"Waveform {i} Arm Flag", num=i)
|
||||
# self._make_csr("wf_halt_on_finish", CSRStorage, 1, f"Waveform {i} Halt on Finish Flag", num=i)
|
||||
# self._make_csr("wf_finished", CSRStatus, 1, f"Waveform {i} Finished Flag", num=i)
|
||||
# self._make_csr("wf_running", CSRStatus, 1, f"Waveform {i} Running Flag", num=i)
|
||||
# self._make_csr("wf_time_to_wait", CSRStorage, 16, f"Waveform {i} Wait Time", num=i)
|
||||
# self._make_csr("wf_refresh_start", CSRStorage, 1, f"Waveform {i} Data Refresh Start Flag", num=i)
|
||||
# self._make_csr("wf_refresh_finished", CSRStatus, 1, f"Waveform {i} Data Refresh Finished Flag", num=i)
|
||||
# self._make_csr("wf_start_addr", CSRStorage, 32, f"Waveform {i} Data Addr", num=i)
|
||||
#
|
||||
# port = sdram.crossbar.get_port()
|
||||
# setattr(self, f"wf_sdram_{i}", LiteDRAMDMAReader(port))
|
||||
# cur_sdram = getattr(self, f"wf_sdram_{i}")
|
||||
#
|
||||
# self.kwargs[f"o_wf_ram_dma_addr_{i}"] = cur_sdram.sink.address
|
||||
# self.kwargs[f"i_wf_ram_word_{i}"] = cur_sdram.source.data
|
||||
# self.kwargs[f"o_wf_ram_read_{i}"] = cur_sdram.sink.valid
|
||||
# self.kwargs[f"i_wf_ram_valid_{i}"] = cur_sdram.source.valid
|
||||
|
||||
self._make_csr("adc_finished", CSRStatus, 1, f"ADC {i} Finished Flag", num=i)
|
||||
self._make_csr("adc_arm", CSRStorage, 1, f"ADC {i} Arm Flag", num=i)
|
||||
self._make_csr("adc_recv_buf", CSRStatus, 32, f"ADC {i} Received Data", num=i)
|
||||
|
||||
self._make_csr("cl_in_loop", CSRStatus, 1, "Control Loop Loop Enabled Flag")
|
||||
self._make_csr("cl_cmd", CSRStorage, 8, "Control Loop Command Input")
|
||||
self._make_csr("cl_word_in", CSRStorage, 64, "Control Loop Data Input")
|
||||
self._make_csr("cl_word_out", CSRStatus, 64, "Control Loop Data Output")
|
||||
self._make_csr("cl_start_cmd", CSRStorage, 1, "Control Loop Command Start Flag")
|
||||
self._make_csr("cl_finish_cmd", CSRStatus, 1, "Control Loop Command Finished Flag")
|
||||
self._make_csr("cl_z_report", CSRStatus, 1, "Control Loop Z Setting")
|
||||
for reg in mmio_descr.registers:
|
||||
if reg.num > 1:
|
||||
for i in range(0,reg.num):
|
||||
self._make_csr(reg,i)
|
||||
else:
|
||||
self._make_csr(reg)
|
||||
|
||||
self.kwargs["i_clk"] = clk
|
||||
self.kwargs["i_rst_L"] = ~platform.request("module_reset")
|
||||
|
|
@ -209,14 +178,8 @@ class Base(Module, AutoCSR):
|
|||
self.kwargs["o_adc_conv"] = platform.request("adc_conv")
|
||||
self.kwargs["i_adc_sdo"] = platform.request("adc_sdo")
|
||||
self.kwargs["o_adc_sck"] = platform.request("adc_sck")
|
||||
# self.kwargs["o_test_clock"] = platform.request("test_clock")
|
||||
self.kwargs["o_set_low"] = platform.request("differntial_output_low")
|
||||
|
||||
""" Dump all MMIO pins to a JSON file with their exact bit widths. """
|
||||
with open("csr_bitwidth.json", mode='w') as f:
|
||||
import json
|
||||
json.dump(self.csrdict, f)
|
||||
|
||||
self.specials += Instance("base", **self.kwargs)
|
||||
|
||||
# Clock and Reset Generator
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@ platform-runcmd = echo LiteX/VexRiscv
|
|||
|
||||
PLATFORM_RISCV_XLEN = 32
|
||||
PLATFORM_RISCV_ABI = ilp32
|
||||
#PLATFORM_RISCV_ISA = rv32ima ## XXX: Broken on new binutils
|
||||
PLATFORM_RISCV_ISA = rv32ima_zicsr_zifencei
|
||||
PLATFORM_RISCV_CODE_MODEL = medany
|
||||
platform-objs-y += platform.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue