diff options
| author |  Peter McGoron
| 2022-10-23 12:37:07 -0400 |
|---|---|---|
| committer | Peter McGoron
| 2022-10-23 12:37:07 -0400 |
| commit | 039507d13ab003ad432eb903224dcf7242cc9c23 (patch) | |
| tree | 45da3812a0fdc61a586ae22057f2fe02a0fb7893 /spi_master_ss_template.v | |
| parent | factor out code (diff) | |
test master with SS
Diffstat (limited to 'spi_master_ss_template.v')
| -rw-r--r-- | spi_master_ss_template.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/spi_master_ss_template.v b/spi_master_ss_template.v index 27a4b85..e2e0cc4 100644 --- a/spi_master_ss_template.v +++ b/spi_master_ss_template.v @@ -7,7 +7,7 @@ module `SPI_MASTER_SS_NAME parameter WID = 24, parameter WID_LEN = 5, parameter CYCLE_HALF_WAIT = 1, - parameter CYCLE_HALF_WAIT_TIMER_LEN = 3, + parameter TIMER_LEN = 3, parameter SS_WAIT = 1, parameter SS_WAIT_TIMER_LEN = 2, @@ -33,13 +33,13 @@ module `SPI_MASTER_SS_NAME reg ss = 0; reg arm_master = 0; -assign ss_L = ss; +assign ss_L = !ss; `SPI_MASTER_NAME #( .WID(WID), .WID_LEN(WID_LEN), .CYCLE_HALF_WAIT(CYCLE_HALF_WAIT), - .TIMER_LEN(CYCLE_HALF_WAIT_TIMER_LEN), + .TIMER_LEN(TIMER_LEN), .POLARITY(POLARITY), .PHASE(PHASE) ) master ( @@ -62,6 +62,7 @@ localparam WAIT_ON_SS = 1; localparam WAIT_ON_MASTER = 2; localparam WAIT_ON_ARM_DEASSERT = 3; reg [2:0] state = WAIT_ON_ARM; +reg [SS_WAIT_TIMER_LEN-1:0] timer = 0; task master_arm(); arm_master <= 1; @@ -92,6 +93,7 @@ always @ (posedge clk) begin WAIT_ON_MASTER: begin if (finished) begin state <= WAIT_ON_ARM_DEASSERT; + ss <= 0; end end WAIT_ON_ARM_DEASSERT: begin @@ -100,6 +102,7 @@ always @ (posedge clk) begin arm_master <= 0; end end + endcase end endmodule |