start spi master and slave with testbench

1 files changed, 45 insertions, 0 deletions

diff --git a/test_spi_write_read_mode0.cpp b/test_spi_write_read_mode0.cpp
new file mode 100644
index 0000000..bbbf03c
--- /dev/null
+++ b/test_spi_write_read_mode0.cpp
@@ -0,0 +1,45 @@
+#include <stdio.h>
+#include <verilated.h>
+#include "Vtest_spi_write_read_mode0.h"
+using TopModule = Vtest_spi_write_read_mode0;
+
+VerilatedContext *ctx;
+TopModule *sim;
+
+static void progress() {
+	sim->eval();
+	ctx->timeInc(1);
+	sim->clk = !sim->clk;
+}
+
+static void progress_n(int f) {
+	for (int i = 0; i < f; i++)
+		progress();
+}
+
+int main(int argc, char **argv) {
+	ctx = new VerilatedContext;
+	ctx->traceEverOn(true);
+	ctx->commandArgs(argc, argv);
+	sim = new TopModule(ctx);
+	sim->ss = 0;
+	sim->clk = 0;
+	sim->activate = 0;
+
+	progress_n(8);
+	sim->ss = 1;
+	progress();
+
+	sim->data_ctrl = 0b110011011111001100011111;
+	sim->activate = 1;
+
+	while (!sim->master_finished)
+		progress();
+	progress_n(5);
+	sim->ss = 0;
+	progress_n(5);
+
+	sim->final();
+	delete sim;
+	return 0;
+}