start spi master and slave with testbench

1 files changed, 58 insertions, 0 deletions

diff --git a/test_spi_write_read_mode0.v b/test_spi_write_read_mode0.v
new file mode 100644
index 0000000..56be197
--- /dev/null
+++ b/test_spi_write_read_mode0.v
@@ -0,0 +1,58 @@
+module test_spi_write_read_mode0
+(
+	input clk,
+	input [23:0] data_ctrl,
+	input activate,
+	input ss,
+	output master_finished,
+	output slave_finished,
+	output slave_error
+);
+
+wire miso;
+wire mosi;
+wire sck;
+wire ss_L = !ss;
+
+reg [23:0] from_slave_data;
+
+spi_master master
+(
+	.clk(clk),
+	.to_slave(data_ctrl),
+	.from_slave(from_slave_data),
+	.miso(miso),
+	.mosi(mosi),
+	.sck_wire(sck),
+	.finished(master_finished),
+	.arm(activate)
+);
+
+reg [23:0] data_from_master;
+reg [23:0] data_to_master = 24'b111011011100010101010101;
+
+spi_slave spi_slave
+(
+	.clk(clk),
+	.sck(sck),
+	.ss_L(ss_L),
+	.from_master(data_from_master),
+	.to_master(data_to_master),
+	.mosi(mosi),
+	.miso(miso),
+	.finished(slave_finished),
+	.err(slave_error)
+);
+
+always @ (posedge clk) begin
+	if (slave_finished) begin
+		data_to_master <= data_from_master;
+	end
+end
+
+initial begin
+	$dumpfile("test_spi_write_read_mode0.vcd");
+	$dumpvars();
+end
+
+endmodule