rewrite entire test harness

1 files changed, 54 insertions, 0 deletions

diff --git a/tests/mk.sh b/tests/mk.sh
new file mode 100755
index 0000000..f907668
--- /dev/null
+++ b/tests/mk.sh
@@ -0,0 +1,54 @@
+#!/bin/sh
+
+run_test() {
+	POL=$1
+	PHASE=$2
+	MASTER_TYPE=$3
+	SLAVE_TYPE=$4
+	DIR=$5
+	WID=$6
+	MODS=$7
+	EXTARG=$8
+	WIDLEN=$(printf "import math\nprint(math.floor(math.log2($WID) + 1))" | python3 -)
+
+	verilator --cc --exe -I.. -Wall -Wno-unused --trace \
+		--top-module simtop \
+		-GPOLARITY=$POL -GPHASE=$PHASE -GWID=$WID -CFLAGS -DWID=$WID \
+		-GWID_LEN=$WIDLEN \
+		-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
+		--Mdir $DIR \
+		$EXTARG \
+		simtop.v write_read.cpp $MODS
+
+	cd "$DIR"
+	make -f Vsimtop.mk
+	./Vsimtop
+}
+
+for POL in 0 1; do
+	for PHASE in 0 1; do
+		( \
+			run_test $POL $PHASE \
+			spi_master spi_slave \
+			simtop_$POL$PHASE 24 \
+			"../spi_master.v ../spi_slave.v"
+		)
+
+		( \
+			run_test $POL $PHASE \
+			spi_master_no_write spi_slave_no_read \
+			simtop_no_write_$POL$PHASE 24 \
+			"../spi_master_no_write.v ../spi_slave_no_read.v" \
+			"-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE"
+		)
+
+		( \
+			run_test $POL $PHASE \
+			spi_master_no_read spi_slave_no_write \
+			simtop_no_read_$POL$PHASE 24 \
+			"../spi_master_no_read.v ../spi_slave_no_write.v" \
+			"-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ"
+		)
+
+	done
+done