diff options
| author |  Peter McGoron
| 2022-10-23 12:37:07 -0400 |
|---|---|---|
| committer | Peter McGoron
| 2022-10-23 12:37:07 -0400 |
| commit | 039507d13ab003ad432eb903224dcf7242cc9c23 (patch) | |
| tree | 45da3812a0fdc61a586ae22057f2fe02a0fb7893 /tests/simtop.v | |
| parent | factor out code (diff) | |
test master with SS
Diffstat (limited to 'tests/simtop.v')
| -rw-r--r-- | tests/simtop.v | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/tests/simtop.v b/tests/simtop.v index d47a802..a1461bc 100644 --- a/tests/simtop.v +++ b/tests/simtop.v @@ -21,7 +21,9 @@ module simtop output [WID-1:0] from_slave, `endif input activate, +`ifndef SPI_MASTER_SS input ss, +`endif input rdy, output master_finished, output err @@ -36,18 +38,27 @@ wire mosi; `endif wire sck; -wire ss_L = !ss; +wire ss_L; + +`ifndef SPI_MASTER_SS +assign ss_L = !ss; +`endif reg slave_finished; reg slave_error; `SPI_MASTER_TYPE #( +`ifdef SPI_MASTER_SS + .SS_WAIT(5), + .SS_WAIT_TIMER_LEN(3), +`endif + .CYCLE_HALF_WAIT(5), + .TIMER_LEN(3), .POLARITY(POLARITY), .PHASE(PHASE), .WID(WID), - .WID_LEN(WID_LEN), - .CYCLE_HALF_WAIT(5) + .WID_LEN(WID_LEN) ) master ( .clk(clk), `ifndef SPI_MASTER_NO_WRITE @@ -58,6 +69,9 @@ reg slave_error; .from_slave(from_slave), .miso(miso), `endif +`ifdef SPI_MASTER_SS + .ss_L(ss_L), +`endif .sck_wire(sck), .finished(master_finished), .arm(activate) @@ -85,4 +99,11 @@ reg slave_error; .err(err) ); +/* +initial begin + $dumpfile(`VCDFILE); + $dumpvars; +end +*/ + endmodule |