clean up tests

1 files changed, 16 insertions, 23 deletions

diff --git a/tests/simtop.v b/tests/simtop.v
index 1e6662a..c280633 100644
--- a/tests/simtop.v
+++ b/tests/simtop.v
@@ -1,11 +1,13 @@
-/* (c) Peter McGoron 2022
- * This Source Code Form is subject to the terms of the Mozilla Public
- * License, v.2.0. If a copy of the MPL was not distributed with this
- * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+/* (c) Peter McGoron 2022-2024 v0.4
+ *
+ * This code is disjunctively dual-licensed under the MPL v2.0, or the
+ * CERN-OHL-W v2.
  */
 
 module simtop
 #(
+	parameter ENABLE_MOSI = 1,
+	parameter ENABLE_MISO = 1,
 	parameter POLARITY = 0,
 	parameter PHASE = 0,
 	parameter WID = 24,
@@ -13,14 +15,13 @@ module simtop
 ) (
 	input clk,
 	input rst_L,
-`ifndef SPI_MASTER_NO_WRITE
+
 	input [WID-1:0] master_to_slave,
 	output [WID-1:0] from_master,
-`endif
-`ifndef SPI_MASTER_NO_READ
+
 	input [WID-1:0] slave_to_master,
 	output [WID-1:0] from_slave,
-`endif
+
 	input activate,
 `ifndef SPI_MASTER_SS
 	input ss,
@@ -31,13 +32,9 @@ module simtop
 	output err
 );
 
-`ifndef SPI_MASTER_NO_READ
 wire miso;
-`endif
 
-`ifndef SPI_MASTER_NO_WRITE
 wire mosi;
-`endif
 
 wire sck;
 wire ss_L;
@@ -46,8 +43,8 @@ wire ss_L;
 assign ss_L = !ss;
 `endif
 
-reg slave_finished;
-reg slave_error;
+wire slave_finished;
+wire slave_error;
 
 `SPI_MASTER_TYPE
 #(
@@ -55,6 +52,8 @@ reg slave_error;
 	.SS_WAIT(5),
 	.SS_WAIT_TIMER_LEN(3),
 `endif
+	.ENABLE_MOSI(ENABLE_MOSI),
+	.ENABLE_MISO(ENABLE_MISO),
 	.CYCLE_HALF_WAIT(5),
 	.TIMER_LEN(3),
 	.POLARITY(POLARITY),
@@ -64,14 +63,10 @@ reg slave_error;
 ) master (
 	.clk(clk),
 	.rst_L(rst_L),
-`ifndef SPI_MASTER_NO_WRITE
 	.to_slave(master_to_slave),
 	.mosi(mosi),
-`endif
-`ifndef SPI_MASTER_NO_READ
 	.from_slave(from_slave),
 	.miso(miso),
-`endif
 `ifdef SPI_MASTER_SS
 	.ss_L(ss_L),
 `endif
@@ -81,7 +76,9 @@ reg slave_error;
 	.arm(activate)
 );
 
-`SPI_SLAVE_TYPE #(
+spi_slave #(
+	.ENABLE_MOSI(ENABLE_MOSI),
+	.ENABLE_MISO(ENABLE_MISO),
 	.POLARITY(POLARITY),
 	.PHASE(PHASE),
 	.WID(WID),
@@ -91,14 +88,10 @@ reg slave_error;
 	.rst_L(rst_L),
 	.sck(sck),
 	.ss_L(ss_L),
-`ifndef SPI_MASTER_NO_WRITE
 	.from_master(from_master),
 	.mosi(mosi),
-`endif
-`ifndef SPI_MASTER_NO_READ
 	.to_master(slave_to_master),
 	.miso(miso),
-`endif
 	.finished(slave_finished),
 	.rdy(rdy),
 	.err(err)