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authorGravatar Peter McGoron 2023-04-20 19:10:04 +0000
committerGravatar Peter McGoron 2023-04-20 19:10:04 +0000
commit1c6672e618e901c2933cf9e81d97471f4ef560d3 (patch)
treeffba660091a7ab1a494bddcf8a6b9618e554f5e5 /tests
parentadd ready_to_arm to indiciate when the module can accept another command (diff)
add reset pin
Diffstat (limited to 'tests')
-rw-r--r--tests/simtop.v3
-rw-r--r--tests/write_read.cpp35
2 files changed, 37 insertions, 1 deletions
diff --git a/tests/simtop.v b/tests/simtop.v
index 71981a8..1e6662a 100644
--- a/tests/simtop.v
+++ b/tests/simtop.v
@@ -12,6 +12,7 @@ module simtop
parameter WID_LEN = 5
) (
input clk,
+ input rst_L,
`ifndef SPI_MASTER_NO_WRITE
input [WID-1:0] master_to_slave,
output [WID-1:0] from_master,
@@ -62,6 +63,7 @@ reg slave_error;
.WID_LEN(WID_LEN)
) master (
.clk(clk),
+ .rst_L(rst_L),
`ifndef SPI_MASTER_NO_WRITE
.to_slave(master_to_slave),
.mosi(mosi),
@@ -86,6 +88,7 @@ reg slave_error;
.WID_LEN(WID_LEN)
) slave (
.clk(clk),
+ .rst_L(rst_L),
.sck(sck),
.ss_L(ss_L),
`ifndef SPI_MASTER_NO_WRITE
diff --git a/tests/write_read.cpp b/tests/write_read.cpp
index 74a94ce..be02e57 100644
--- a/tests/write_read.cpp
+++ b/tests/write_read.cpp
@@ -31,6 +31,17 @@ static void progress_n(int f) {
progress();
}
+static void test_reset_pin(void) {
+ sim->rst_L = 0;
+ progress();
+ sim->rdy = 1;
+ sim->activate = 1;
+
+ progress_n(200);
+ assert(!sim->master_finished);
+ sim->rst_L = 1;
+}
+
static void test_cross_transfer(unsigned m2s, unsigned s2m) {
#ifndef SPI_MASTER_NO_WRITE
sim->master_to_slave = m2s;
@@ -39,6 +50,7 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) {
sim->slave_to_master = s2m;
#endif
+ sim->rst_L = 1;
progress();
SET_SS(sim, 1);
sim->rdy = 1;
@@ -74,6 +86,19 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) {
#endif
}
+static void test_interrupted(unsigned m2s, unsigned s2m) {
+ sim->rst_L = 1;
+ progress();
+
+ sim->rdy = 1;
+ sim->activate = 1;
+ progress_n(6);
+ sim->rst_L = 0;
+ progress_n(100);
+ sim->rst_L = 1;
+ test_cross_transfer(m2s, s2m);
+}
+
int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
@@ -84,13 +109,21 @@ int main(int argc, char **argv) {
sim->activate = 0;
sim->rdy = 0;
+ test_reset_pin();
test_cross_transfer(0b101010101010101010101010, 0b010101010101010101010101);
test_cross_transfer(0b110011001100110011001100, 0b001100110011001100110011);
+ test_reset_pin();
for (int i = 0; i < 10000; i++) {
unsigned m2s = rand() & ((1 << WID) - 1);
unsigned s2m = rand() & ((1 << WID) - 1);
- test_cross_transfer(m2s, s2m);
+ if (i % (((rand() + 1) % 32) + 1) == 0)
+ test_interrupted(m2s, s2m);
+ else
+ test_cross_transfer(m2s, s2m);
+ if (i % (((rand() + 1) % 64) + 1) == 0)
+ test_reset_pin();
+
}
sim->final();