move tests

6 files changed, 191 insertions, 0 deletions

diff --git a/tests/mode00.cpp b/tests/mode00.cpp
new file mode 100644
index 0000000..4ba98dd
--- /dev/null
+++ b/tests/mode00.cpp
@@ -0,0 +1,3 @@
+#include "Vmode00.h"
+using TopModule = Vmode00;
+#include "write_read.cpp"
diff --git a/tests/mode00.v b/tests/mode00.v
new file mode 100644
index 0000000..2a037cf
--- /dev/null
+++ b/tests/mode00.v
@@ -0,0 +1,34 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module mode00 (
+	input clk,
+	input [23:0] data_ctrl,
+	input activate,
+	input ss,
+	input rdy,
+	output master_finished
+);
+
+spi_write_read
+#(
+	.POLARITY(0),
+	.PHASE(0)
+) base (
+	.clk(clk),
+	.data_ctrl(data_ctrl),
+	.activate(activate),
+	.master_finished(master_finished),
+	.ss(ss),
+	.rdy(rdy)
+);
+
+initial begin
+	$dumpfile("mode00.vcd");
+	$dumpvars();
+end
+
+endmodule
diff --git a/tests/run.sh b/tests/run.sh
new file mode 100755
index 0000000..ea99836
--- /dev/null
+++ b/tests/run.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+for i in 00; do
+	make -f run_mode.makefile MODE="$i"
+done
diff --git a/tests/run_mode.makefile b/tests/run_mode.makefile
new file mode 100644
index 0000000..31b6644
--- /dev/null
+++ b/tests/run_mode.makefile
@@ -0,0 +1,25 @@
+# (c) Peter McGoron 2022
+# This Source Code Form is subject to the terms of the Mozilla Public
+# License, v.2.0. If a copy of the MPL was not distributed with this
+# file, You can obtain one at https://mozilla.org/MPL/2.0/.
+
+TESTBENCH_BASE=mode${MODE}
+AUXFILES=../spi_master.v ../spi_slave.v
+
+CPP_TESTBENCH=${TESTBENCH_BASE}.cpp
+WAVEFILE=${TESTBENCH_BASE}.vcd
+
+FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
+
+all: obj_dir/V${TESTBENCH_BASE}
+	./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
+
+obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
+	verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
+obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
+	make -C obj_dir -f V${TESTBENCH_BASE}.mk
+
+run:
+	./obj_dir/V${TESTBENCH_CASE}
+clean:
+	$(RM) obj_dir/*
diff --git a/tests/spi_write_read.v b/tests/spi_write_read.v
new file mode 100644
index 0000000..8045a1c
--- /dev/null
+++ b/tests/spi_write_read.v
@@ -0,0 +1,65 @@
+/* (c) Peter McGoron 2022
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v.2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at https://mozilla.org/MPL/2.0/.
+ */
+
+module spi_write_read
+#(
+	parameter POLARITY = 0,
+	parameter PHASE = 0
+)
+(
+	input clk,
+	input [23:0] data_ctrl,
+	input activate,
+	input ss,
+	input rdy,
+	output master_finished
+);
+
+wire miso;
+wire mosi;
+wire sck;
+wire ss_L = !ss;
+
+reg [23:0] from_slave_data;
+reg slave_finished;
+reg slave_error;
+
+spi_master master
+(
+	.clk(clk),
+	.to_slave(data_ctrl),
+	.from_slave(from_slave_data),
+	.miso(miso),
+	.mosi(mosi),
+	.sck_wire(sck),
+	.finished(master_finished),
+	.arm(activate)
+);
+
+reg [23:0] data_from_master;
+reg [23:0] data_to_master = 24'b111011011100010101010101;
+
+spi_slave slave
+(
+	.clk(clk),
+	.sck(sck),
+	.ss_L(ss_L),
+	.from_master(data_from_master),
+	.to_master(data_to_master),
+	.mosi(mosi),
+	.miso(miso),
+	.finished(slave_finished),
+	.rdy(rdy),
+	.err(slave_error)
+);
+
+always @ (posedge clk) begin
+	if (slave_finished) begin
+		data_to_master <= data_from_master;
+	end
+end
+
+endmodule
diff --git a/tests/write_read.cpp b/tests/write_read.cpp
new file mode 100644
index 0000000..457180a
--- /dev/null
+++ b/tests/write_read.cpp
@@ -0,0 +1,59 @@
+#include <stdio.h>
+#include <verilated.h>
+
+VerilatedContext *ctx;
+TopModule *sim;
+
+static void progress() {
+	sim->eval();
+	ctx->timeInc(1);
+	sim->clk = !sim->clk;
+}
+
+static void progress_n(int f) {
+	for (int i = 0; i < f; i++)
+		progress();
+}
+
+int main(int argc, char **argv) {
+	ctx = new VerilatedContext;
+	ctx->traceEverOn(true);
+	ctx->commandArgs(argc, argv);
+	sim = new TopModule(ctx);
+	sim->ss = 0;
+	sim->clk = 0;
+	sim->activate = 0;
+	sim->rdy = 0;
+
+	progress_n(8);
+	sim->ss = 1;
+	sim->rdy = 1;
+	progress();
+
+	sim->data_ctrl = 0b110011011111001100011111;
+	sim->activate = 1;
+
+	while (!sim->master_finished)
+		progress();
+	progress_n(5);
+	sim->activate = 0;
+	sim->ss = 0;
+	sim->rdy = 0;
+	progress_n(5);
+
+	sim->data_ctrl = 0xFE3456;
+	sim->activate = 1;
+	sim->ss = 1;
+	sim->rdy = 1;
+	while (!sim->master_finished)
+		progress();
+	progress_n(5);
+	sim->activate = 0;
+	sim->ss = 0;
+	sim->rdy = 0;
+	progress_n(5);
+
+	sim->final();
+	delete sim;
+	return 0;
+}