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/* (c) Peter McGoron 2022
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v.2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
module spi_write_read
#(
parameter POLARITY = 0,
parameter PHASE = 0
)
(
input clk,
input [23:0] data_ctrl,
input activate,
input ss,
input rdy,
output master_finished
);
wire miso;
wire mosi;
wire sck;
wire ss_L = !ss;
reg [23:0] from_slave_data;
reg slave_finished;
reg slave_error;
spi_master
#(
.POLARITY(POLARITY),
.PHASE(PHASE)
) master (
.clk(clk),
.to_slave(data_ctrl),
.from_slave(from_slave_data),
.miso(miso),
.mosi(mosi),
.sck_wire(sck),
.finished(master_finished),
.arm(activate)
);
reg [23:0] data_from_master;
reg [23:0] data_to_master = 24'b111011011100010101010101;
spi_slave #(
.POLARITY(POLARITY),
.PHASE(PHASE)
) slave (
.clk(clk),
.sck(sck),
.ss_L(ss_L),
.from_master(data_from_master),
.to_master(data_to_master),
.mosi(mosi),
.miso(miso),
.finished(slave_finished),
.rdy(rdy),
.err(slave_error)
);
always @ (posedge clk) begin
if (slave_finished) begin
data_to_master <= data_from_master;
end
end
endmodule
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