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#include <stdio.h>
#include <verilated.h>
#include "Vsimtop.h"
Vsimtop *sim;
#ifdef SPI_MASTER_SS
# define SET_SS(mod, v)
#else
# define SET_SS(mod,v) ((mod)->ss = (v))
#endif
uint32_t main_time = 0;
double sc_time_stamp() {
return main_time;
}
static void progress() {
sim->eval();
main_time++;
sim->clk = !sim->clk;
sim->eval();
main_time++;
sim->clk = !sim->clk;
}
static void progress_n(int f) {
for (int i = 0; i < f; i++)
progress();
}
static void test_cross_transfer(unsigned m2s, unsigned s2m) {
#ifndef SPI_MASTER_NO_WRITE
sim->master_to_slave = m2s;
#endif
#ifndef SPI_MASTER_NO_READ
sim->slave_to_master = s2m;
#endif
progress();
SET_SS(sim, 1);
sim->rdy = 1;
sim->activate = 1;
progress();
while (!sim->master_finished)
progress();
progress_n(5);
sim->activate = 0;
SET_SS(sim, 0);
sim->rdy = 0;
progress_n(5);
if (sim->err) {
printf("slave error\n");
}
#ifndef SPI_MASTER_NO_WRITE
if (sim->master_to_slave != sim->from_master) {
printf("(m2s) %lx != %lx\n", sim->master_to_slave, sim->from_master);
}
#endif
#ifndef SPI_MASTER_NO_READ
if (sim->slave_to_master != sim->from_slave) {
printf("(m2s) %lx != %lx\n", sim->slave_to_master, sim->from_slave);
}
#endif
}
int main(int argc, char **argv) {
int r = 0;
(void)r;
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
sim = new Vsimtop;
SET_SS(sim, 0);
sim->clk = 0;
sim->activate = 0;
sim->rdy = 0;
test_cross_transfer(0b101010101010101010101010, 0b010101010101010101010101);
test_cross_transfer(0b110011001100110011001100, 0b001100110011001100110011);
for (int i = 0; i < 10000; i++) {
unsigned m2s = rand() & ((1 << WID) - 1);
unsigned s2m = rand() & ((1 << WID) - 1);
test_cross_transfer(m2s, s2m);
}
sim->final();
delete sim;
return r;
}
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