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| author | 2024-02-20 20:34:10 -0500 | |
|---|---|---|
| committer | 2024-02-20 20:34:10 -0500 | |
| commit | 4bcefafb697c27501cda3cb6f1584df78d9011bc (patch) | |
| tree | f4aa662ee9eef6c02dd7a13301a1d61247210c82 /xorshift.v | |
Diffstat (limited to '')
| -rw-r--r-- | xorshift.v | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/xorshift.v b/xorshift.v new file mode 100644 index 0000000..1b57a19 --- /dev/null +++ b/xorshift.v @@ -0,0 +1,42 @@ +/* + * Copyright 2024 Peter McGoron + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module xorshift ( + input clk, + output [64-1:0] data +); + +reg [64-1:0] state = 64'd88172645463325252; +assign data = state; + +always @ (posedge clk) begin +`define X_1 (state ^ (state << 13)) +`define X_2 (`X_1 ^ (`X_1 >> 7)) + state <= (`X_2 ^ (`X_2 << 17)); +end + +endmodule |
