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Add supervisor support in the ExternalInterruptArrayPlugin

This commit is contained in:
Charles Papon 2019-05-06 16:23:43 +02:00
parent 3094f8b349
commit 01db217ab9
2 changed files with 16 additions and 7 deletions
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2
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -310,7 +310,7 @@ trait IContextSwitching{
def isContextSwitching : Bool def isContextSwitching : Bool
} }
class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
import config._ import config._
import CsrAccess._ import CsrAccess._

15
src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
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@ -3,7 +3,11 @@ package vexriscv.plugin
import spinal.core._ import spinal.core._
import vexriscv.VexRiscv import vexriscv.VexRiscv
class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC0, pendingsCsrId : Int = 0xFC0) extends Plugin[VexRiscv]{ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32,
machineMaskCsrId : Int = 0xBC0,
machinePendingsCsrId : Int = 0xFC0,
supervisorMaskCsrId : Int = 0x9C0,
supervisorPendingsCsrId : Int = 0xDC0) extends Plugin[VexRiscv]{
var externalInterruptArray : Bits = null var externalInterruptArray : Bits = null
override def setup(pipeline: VexRiscv): Unit = { override def setup(pipeline: VexRiscv): Unit = {
@ -12,10 +16,15 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC
override def build(pipeline: VexRiscv): Unit = { override def build(pipeline: VexRiscv): Unit = {
val csr = pipeline.service(classOf[CsrPlugin]) val csr = pipeline.service(classOf[CsrPlugin])
val externalInterruptArrayBuffer = RegNext(externalInterruptArray)
def gen(maskCsrId : Int, pendingsCsrId : Int, interruptPin : Bool) = new Area {
val mask = Reg(Bits(arrayWidth bits)) init(0) val mask = Reg(Bits(arrayWidth bits)) init(0)
val pendings = mask & RegNext(externalInterruptArray) val pendings = mask & externalInterruptArrayBuffer
csr.externalInterrupt.setAsDirectionLess() := pendings.orR interruptPin.setAsDirectionLess() := pendings.orR
csr.rw(maskCsrId, mask) csr.rw(maskCsrId, mask)
csr.r(pendingsCsrId, pendings) csr.r(pendingsCsrId, pendings)
} }
gen(machineMaskCsrId, machinePendingsCsrId, csr.externalInterrupt)
if(csr.config.supervisorGen) gen(supervisorMaskCsrId, supervisorPendingsCsrId, csr.externalInterruptS)
}
} }