Add supervisor support in the ExternalInterruptArrayPlugin
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@ -310,7 +310,7 @@ trait IContextSwitching{
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def isContextSwitching : Bool
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}
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class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
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class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
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import config._
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import CsrAccess._
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@ -3,7 +3,11 @@ package vexriscv.plugin
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import spinal.core._
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import vexriscv.VexRiscv
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class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC0, pendingsCsrId : Int = 0xFC0) extends Plugin[VexRiscv]{
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class ExternalInterruptArrayPlugin(arrayWidth : Int = 32,
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machineMaskCsrId : Int = 0xBC0,
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machinePendingsCsrId : Int = 0xFC0,
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supervisorMaskCsrId : Int = 0x9C0,
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supervisorPendingsCsrId : Int = 0xDC0) extends Plugin[VexRiscv]{
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var externalInterruptArray : Bits = null
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override def setup(pipeline: VexRiscv): Unit = {
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@ -12,10 +16,15 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC
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override def build(pipeline: VexRiscv): Unit = {
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val csr = pipeline.service(classOf[CsrPlugin])
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val externalInterruptArrayBuffer = RegNext(externalInterruptArray)
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def gen(maskCsrId : Int, pendingsCsrId : Int, interruptPin : Bool) = new Area {
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val mask = Reg(Bits(arrayWidth bits)) init(0)
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val pendings = mask & RegNext(externalInterruptArray)
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csr.externalInterrupt.setAsDirectionLess() := pendings.orR
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val pendings = mask & externalInterruptArrayBuffer
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interruptPin.setAsDirectionLess() := pendings.orR
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csr.rw(maskCsrId, mask)
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csr.r(pendingsCsrId, pendings)
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}
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gen(machineMaskCsrId, machinePendingsCsrId, csr.externalInterrupt)
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if(csr.config.supervisorGen) gen(supervisorMaskCsrId, supervisorPendingsCsrId, csr.externalInterruptS)
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}
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}
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