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VexRiscv
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Got the MMU refilling itself with datacache cached memory access instead of io accesses

This commit is contained in:
Charles Papon 2019-04-03 14:32:21 +02:00
parent 8be40e637b
commit 066f562c5e
3 changed files with 17 additions and 7 deletions
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9
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -257,7 +257,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
cache.io.cpu.execute.args.wr := dBusAccess.cmd.write
cache.io.cpu.execute.args.data := dBusAccess.cmd.data
cache.io.cpu.execute.args.size := dBusAccess.cmd.size
cache.io.cpu.execute.args.forceUncachedAccess := True //TODO Cached and redo management
cache.io.cpu.execute.args.forceUncachedAccess := False
if(genAtomic) cache.io.cpu.execute.args.isAtomic := False
cache.io.cpu.execute.address := dBusAccess.cmd.address //Will only be 12 muxes
forceDatapath := True
@ -269,16 +269,19 @@ class DBusCachedPlugin(config : DataCacheConfig,
mmuBus.cmd.bypassTranslation setWhen(memory.input(IS_DBUS_SHARING))
cache.io.cpu.memory.isValid setWhen(memory.input(IS_DBUS_SHARING))
cache.io.cpu.writeBack.isValid setWhen(writeBack.input(IS_DBUS_SHARING))
dBusAccess.rsp.valid := writeBack.input(IS_DBUS_SHARING) && !cache.io.cpu.writeBack.isWrite && !cache.io.cpu.writeBack.haltIt
dBusAccess.rsp.valid := writeBack.input(IS_DBUS_SHARING) && !cache.io.cpu.writeBack.isWrite && (cache.io.cpu.redo || !cache.io.cpu.writeBack.haltIt)
dBusAccess.rsp.data := cache.io.cpu.writeBack.data
dBusAccess.rsp.error := cache.io.cpu.writeBack.unalignedAccess || cache.io.cpu.writeBack.accessError
dBusAccess.rsp.redo := cache.io.cpu.redo
component.addPrePopTask{() =>
when(forceDatapath){
execute.output(REGFILE_WRITE_DATA) := dBusAccess.cmd.address.asBits
}
memory.input(IS_DBUS_SHARING) init(False)
writeBack.input(IS_DBUS_SHARING) init(False)
when(dBusAccess.rsp.valid){
writeBack.input(IS_DBUS_SHARING).getDrivingReg := False
}
}
}

1
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -497,6 +497,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
dBusAccess.rsp.valid := False
dBusAccess.rsp.data := dBus.rsp.data
dBusAccess.rsp.error := dBus.rsp.error
dBusAccess.rsp.redo := False
switch(state){
is(0){

14
src/main/scala/vexriscv/plugin/MmuPlugin.scala
View File

@ -21,6 +21,7 @@ case class DBusAccessCmd() extends Bundle {
case class DBusAccessRsp() extends Bundle {
val data = Bits(32 bits)
val error = Bool()
val redo = Bool()
}
case class DBusAccess() extends Bundle {
@ -161,7 +162,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
val leaf = pte.R || pte.X
}
val pteBuffer = RegNextWhen(dBusRsp.pte, dBusAccess.rsp.valid)
val pteBuffer = RegNextWhen(dBusRsp.pte, dBusAccess.rsp.valid && !dBusAccess.rsp.redo)
dBusAccess.cmd.valid := False
dBusAccess.cmd.write := False
@ -190,10 +191,12 @@ class MmuPlugin(virtualRange : UInt => Bool,
}
is(State.L1_RSP){
when(dBusAccess.rsp.valid){
state := State.L0_CMD
when(dBusRsp.leaf || dBusRsp.exception){
state := State.IDLE
} otherwise {
state := State.L0_CMD
}
when(dBusAccess.rsp.redo){
state := State.L1_CMD
}
}
}
@ -207,11 +210,14 @@ class MmuPlugin(virtualRange : UInt => Bool,
is(State.L0_RSP){
when(dBusAccess.rsp.valid) {
state := State.IDLE
when(dBusAccess.rsp.redo){
state := State.L0_CMD
}
}
}
}
when(dBusAccess.rsp.valid && (dBusRsp.leaf || dBusRsp.exception)){
when(dBusAccess.rsp.valid && !dBusAccess.rsp.redo && (dBusRsp.leaf || dBusRsp.exception)){
for(port <- ports){
when(portId === port.id) {
port.entryToReplace.increment()