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Fix SMP fence lock when 4 stages CPU

This commit is contained in:
Dolu1990 2020-05-01 12:45:16 +02:00
parent f5f30615ba
commit 09ac23b78f
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -314,7 +314,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
} }
when(arbitration.isValid && (input(MEMORY_FENCE) || aquire)){ when(arbitration.isValid && (input(MEMORY_FENCE) || aquire)){
memory.arbitration.haltByOther := True //Ensure that the fence affect the memory stage instruction by stoping it mmuAndBufferStage.arbitration.haltByOther := True //Ensure that the fence affect the memory stage instruction by stoping it
} }
} }