Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -84,7 +84,7 @@ object BrieySynthesisBench {
 //    )
 //
 //    Bench(rtls, targets, "/eda/tmp/")
-    
+
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
     ) ++ AlteraStdTargets(

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -165,7 +165,7 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
       )
 
       when(arbitration.isValid && input(MEMORY_ENABLE)) {
-        input(REGFILE_WRITE_DATA) := rspFormated
+        output(REGFILE_WRITE_DATA) := rspFormated
       }
    }
   }

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -270,7 +270,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
       )
 
       when(arbitration.isValid && input(MEMORY_ENABLE)) {
-        input(REGFILE_WRITE_DATA) := rspFormated
+        output(REGFILE_WRITE_DATA) := rspFormated
       }
 
       if(!earlyInjection)

src/main/scala/vexriscv/plugin/DivPlugin.scala

@@ -61,7 +61,7 @@ class DivPlugin extends Plugin[VexRiscv]{
        when(arbitration.isValid && input(IS_DIV)) {
          arbitration.haltItself := !divider.io.rsp.valid
 
-         input(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
+         output(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
        }
 
 

src/main/scala/vexriscv/plugin/MulPlugin.scala

@@ -92,10 +92,10 @@ class MulPlugin extends Plugin[VexRiscv]{
       when(arbitration.isValid && input(IS_MUL)){
         switch(input(INSTRUCTION)(13 downto 12)){
           is(B"00"){
-            input(REGFILE_WRITE_DATA) := input(MUL_LOW)(31 downto 0).asBits
+            output(REGFILE_WRITE_DATA) := input(MUL_LOW)(31 downto 0).asBits
           }
           is(B"01",B"10",B"11"){
-            input(REGFILE_WRITE_DATA) := result(63 downto 32).asBits
+            output(REGFILE_WRITE_DATA) := result(63 downto 32).asBits
           }
         }
       }

src/main/scala/vexriscv/plugin/RegFilePlugin.scala

@@ -63,9 +63,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = fals
       import writeBack._
 
       val regFileWrite = global.regFile.writePort.addAttribute(Verilator.public)
-      regFileWrite.valid := input(REGFILE_WRITE_VALID) && arbitration.isFiring
-      regFileWrite.address := input(INSTRUCTION)(rdRange).asUInt
-      regFileWrite.data := input(REGFILE_WRITE_DATA)
+      regFileWrite.valid := output(REGFILE_WRITE_VALID) && arbitration.isFiring
+      regFileWrite.address := output(INSTRUCTION)(rdRange).asUInt
+      regFileWrite.data := output(REGFILE_WRITE_DATA)
 
       //CPU will initialise constant register zero in the first cycle
       regFileWrite.valid setWhen(RegNext(False) init(True))