Update simd_add makefile
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@ -47,14 +47,14 @@ object VexRiscvSynthesisBench {
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val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, fullNoMmu, full)
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val targets = XilinxStdTargets(
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vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
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vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
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) ++ AlteraStdTargets(
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quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64",
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quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64",
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quartusCycloneVPath = "D:/altera_lite/15.1/quartus/bin64"
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quartusCycloneIIPath = null,
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quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
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quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
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)
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Bench(rtls, targets, "E:/tmp/")
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Bench(rtls, targets, "/eda/tmp/")
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}
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}
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@ -75,6 +75,16 @@ object BrieySynthesisBench {
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val rtls = List(briey)
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// val targets = XilinxStdTargets(
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// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
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// ) ++ AlteraStdTargets(
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// quartusCycloneIIPath = null,
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// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
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// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
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// )
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//
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// Bench(rtls, targets, "/eda/tmp/")
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val targets = XilinxStdTargets(
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vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"
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) ++ AlteraStdTargets(
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@ -8,12 +8,12 @@ onChipRam 0x0000000000000000 0x0000000000002000 w !xr
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Linker script and memory map
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LOAD build/src/crt.o
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
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START GROUP
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libc.a
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/../../../../riscv32-unknown-elf/lib/libgloss.a
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
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END GROUP
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LOAD /opt/rv32i/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/libgcc.a
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LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
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0x0000000000000000 . = 0x0
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.crt_section 0x0000000000000000 0xd0
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@ -1,9 +1,9 @@
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PROJ_NAME=custom_simd_add
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RISCV_PATH=/opt/rv32i/
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RISCV_PATH=/opt/riscv/
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CFLAGS += -march=rv32i -mabi=ilp32
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RISCV_NAME = riscv32-unknown-elf
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RISCV_NAME = riscv64-unknown-elf
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RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
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RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
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RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
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