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VexRiscv
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shorter satp export

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Dolu1990 2023-01-16 12:43:01 +01:00 committed by GitHub
parent ed5babaaab
commit 0aa6e0573d
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 12 deletions
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14
src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -93,18 +93,12 @@ class MmuPlugin(ioRange : UInt => Bool,
val sum, mxr, mprv = RegInit(False)
mprv clearWhen(csrService.xretAwayFromMachine)
}
val satp = if(exportSatp) {
new Area {
val mode = out(RegInit(False))
val asid = out(Reg(Bits(9 bits)))
// Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use.
val ppn = out(Reg(UInt(22 bits)))
}
} else {
new Area {
val satp = new Area {
val mode = RegInit(False)
val asid = Reg(Bits(9 bits))
val ppn = Reg(UInt(22 bits))
val ppn = Reg(UInt(22 bits)) // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use.
if(exportSatp) {
out(mode, asid, ppn)
}
}