regression golden ref regfile is now sync with trl boot's random values

wip

src/main/scala/vexriscv/demo/GenFull.scala

@@ -63,7 +63,7 @@ object GenFull extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenFullNoMmu.scala

@@ -55,7 +55,7 @@ object GenFullNoMmu extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala

@@ -56,7 +56,7 @@ object GenFullNoMmuMaxPerf extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala

@@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala

@@ -33,7 +33,7 @@ object GenNoCacheNoMmuMaxPerf extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala

@@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala

@@ -42,7 +42,7 @@ object GenSmallAndProductiveICache extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenSmallest.scala

@@ -28,7 +28,7 @@ object GenSmallest extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true
+          zeroBoot = false
         ),
         new IntAluPlugin,
         new SrcPlugin(

src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala

@@ -33,7 +33,7 @@ object GenSmallestNoCsr extends App{
         ),
         new RegFilePlugin(
           regFileReadyKind = plugin.SYNC,
-          zeroBoot = true,
+          zeroBoot = false,
           writeRfInMemoryStage = false
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -101,8 +101,8 @@ object VexRiscvSynthesisBench {
     }
 
 
-//    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
-    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
+    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
+//    val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
     //      val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
 //    val rtls = List(smallestNoCsr)
 
@@ -113,8 +113,14 @@ object VexRiscvSynthesisBench {
       quartusCycloneVPath  = "/eda/intelFPGA_lite/17.0/quartus/bin"
     ) ++  IcestormStdTargets().take(1)
 
-//    val targets = IcestormStdTargets()
-    Bench(rtls, targets, "/eda/tmp/")
+//    val targets =  AlteraStdTargets(
+//      quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
+//      quartusCycloneVPath  = null
+//    )
+
+
+    //    val targets = IcestormStdTargets()
+    Bench(rtls, targets, "/eda/tmp")
   }
 }
 

src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala

@@ -82,7 +82,7 @@ object VexRiscvAvalonForSim{
           ),
           new RegFilePlugin(
             regFileReadyKind = plugin.SYNC,
-            zeroBoot = true
+            zeroBoot = false
           ),
           new IntAluPlugin,
           new SrcPlugin(

src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala

@@ -80,7 +80,7 @@ object VexRiscvAvalonWithIntegratedJtag{
           ),
           new RegFilePlugin(
             regFileReadyKind = plugin.SYNC,
-            zeroBoot = true
+            zeroBoot = false
           ),
           new IntAluPlugin,
           new SrcPlugin(

src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala

@@ -79,7 +79,7 @@ object VexRiscvCachedWishboneForSim{
           ),
           new RegFilePlugin(
             regFileReadyKind = plugin.SYNC,
-            zeroBoot = true
+            zeroBoot = false
           ),
           new IntAluPlugin,
           new SrcPlugin(

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -735,7 +735,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
       execute plug new Area {
         import execute._
         def previousStage = decode
-        val blockedBySideEffects =  List(memory, writeBack).map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
+        val blockedBySideEffects =  List(memory, writeBack).map(s => s.arbitration.isValid).orR // && s.input(HAS_SIDE_EFFECT)  to improve be less pessimistic
 
         val illegalAccess =  arbitration.isValid && input(IS_CSR)
         val illegalInstruction = False

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -182,7 +182,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
 }
 
 
-class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{
+class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false/*, idempotentRegions : (UInt) => Bool = (x) => False*/) extends Plugin[VexRiscv]{
 
   var dBus  : DBusSimpleBus = null
 

src/test/cpp/regression/main.cpp

@@ -718,6 +718,11 @@ public:
 		logTraces.open (name + ".logTrace");
 		fillSimELements();
 		clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time);
+
+        //Sync register file initial content
+        for(int i = 1;i < 32;i++){
+            riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i];
+        }
 	}
 
 	virtual ~Workspace(){